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asmblurnicolasnoble
asmblur
authored and
nicolasnoble
committed
Added hello.psx. Needs fixing.
1 parent 45242e4 commit 09ceb2b

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9 files changed

+453
-9
lines changed

9 files changed

+453
-9
lines changed

‎.circleci/config.yml

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@@ -18,6 +18,7 @@ jobs:
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name: Build
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command: |
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make -j 2
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make -C src/mips/hello -j 2
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make -C src/mips/shell -j 2
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make -C src/mips/openbios -j 2
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‎src/mips/common.mk

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@@ -2,30 +2,38 @@ PREFIX = mipsel-linux-gnu
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CC = $(PREFIX)-gcc
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TARGETBASE = $(basename $(TARGET))
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ARCHFLAGS = -march=mips1 -mabi=32 -EL -msoft-float -Wa,-msoft-float -fno-pic -mno-shared -mno-abicalls
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CPPFLAGS = -mno-gpopt -fomit-frame-pointer
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CPPFLAGS += -fno-builtin
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CPPFLAGS += $(ARCHFLAGS)
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CPPFLAGS += -I..
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CPPFLAGS += -I.. -I../common/include
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LDFLAGS = -Wl,-Map=$(TARGET).map -nostdlib -T$(LDSCRIPT) -static -Wl,--gc-sections
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LDFLAGS += -Wl,-Map=$(TARGETBASE).map -nostdlib -T$(LDSCRIPT) -static -Wl,--gc-sections -Wl,-v
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LDFLAGS += $(ARCHFLAGS)
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LDFLAGS += -g -O3 -flto
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CPPFLAGS += -g -O3 -flto
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OBJS += $(addsuffix .o, $(basename $(SRCS)))
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all: $(TARGET).bin
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all: $(TARGET)
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clean:
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rm -f $(OBJS) $(TARGET).elf $(TARGET).map $(TARGET).bin
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rm -f $(OBJS) $(TARGETBASE).psx $(TARGETBASE).elf $(TARGET).map $(TARGETBASE).bin $(TARGET)
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$(TARGET).bin: $(TARGET).elf
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$(TARGETBASE).bin: $(TARGETBASE).elf
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$(PREFIX)-objcopy -O binary $< $@
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$(TARGET).elf: $(OBJS)
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$(CC) $(LDFLAGS) -g -o $(TARGET).elf $(OBJS)
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$(TARGETBASE).psx: $(OBJS)
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$(CC) $(LDFLAGS) -g -o $@ $(OBJS)
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$(TARGETBASE).elf: $(OBJS)
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$(CC) $(LDFLAGS) -g -o $(TARGETBASE).elf $(OBJS)
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%.o: %.S
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$(CC) $(CPPFLAGS) -I.. -g -c -o $@ $<
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%.o: %.s
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$(CC) $(ARCHFLAGS) -I.. -g -c -o $@ $<

‎src/mips/common/include/mipsregs.h

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#ifndef _MIPSREGS_H
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#define _MIPSREGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* general registers */
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#define r0 $0
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#define r1 $1
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#define r2 $2
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#define r3 $3
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#define r4 $4
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#define r5 $5
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#define r6 $6
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#define r7 $7
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#define r8 $8
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#define r9 $9
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#define r10 $10
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#define r11 $11
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#define r12 $12
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#define r13 $13
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#define r14 $14
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#define r15 $15
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#define r16 $16
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#define r17 $17
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#define r18 $18
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#define r19 $19
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#define r20 $20
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#define r21 $21
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#define r22 $22
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#define r23 $23
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#define r24 $24
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#define r25 $25
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#define r26 $26
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#define r27 $27
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#define r28 $28
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#define r29 $29
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#define r30 $30
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#define r31 $31
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#define zero $0
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//#define at $1
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#define v0 $2
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#define v1 $3
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#define a0 $4
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16
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#define s1 $17
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#define s2 $18
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#define s3 $19
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#define s4 $20
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24
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#define t9 $25
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#define k0 $26
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#define k1 $27
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#define gp $28
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#define sp $29
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#define s8 $30
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#define fp $30
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#define ra $31
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/* COP0 Registers */
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/* BreakPoint Control */
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#define C0_BPC $3
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/* BreakPoint on Data Access */
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#define C0_BDA $5
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/* BreakPoint on Data Access */
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#define C0_DCIC $7
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#define C0_BADVADDR $8
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#define C0_BDAM $9
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#define C0_BPCM $11
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/* Status Register */
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#define C0_STATUS $12
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/* Cause Register */
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#define C0_CAUSE $13
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/* Error PC Register */
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#define C0_EPC $14
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/* Processor ID */
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#define C0_PRID $15
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// Interrupt Enable(current)
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#define SR_IEC (1 << 0)
103+
// Kernel/User mode(current)
104+
#define SR_KUC (1 << 1)
105+
// Interrupt Enable(previous)
106+
#define SR_IEP (1 << 2)
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// Kernel/User mode(previous)
108+
#define SR_KUP (1 << 3)
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// Interrupt Enable(old)
110+
#define SR_IEO (1 << 4)
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// Kernel/User mode(old)
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#define SR_KUO (1 << 5)
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/* Interrupt Mask 0 */
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#define SR_IMO (1 << 8)
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/* Interrupt Mask 1 */
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#define SR_IM1 (1 << 9)
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/* Interrupt Mask 2 */
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#define SR_IM2 (1 << 10)
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/* Interrupt Mask 3 */
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#define SR_IM3 (1 << 11)
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/* Interrupt Mask 4 */
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#define SR_IM4 (1 << 12)
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/* Interrupt Mask 5 */
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#define SR_IM5 (1 << 13)
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/* Interrupt Mask 6 */
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#define SR_IM6 (1 << 14)
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/* Interrupt Mask 7 */
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#define SR_IM7 (1 << 15)
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/* Isolate Cache */
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#define SR_ISC (1 << 16)
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/* Swap Caches */
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#define SR_SWC (1 << 17)
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/* Parity Zero */
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#define SR_PZ (1 << 18)
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/* Cache Miss */
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#define SR_CM (1 << 19)
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/* Parity Error */
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#define SR_PE (1 << 20)
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/* TLB Shutdown */
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#define SR_TS (1 << 21)
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/* Boot-time Exception Vector */
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#define SR_BEV (1 << 22)
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/* Reverse Endian enable */
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#define SR_RE (1 << 25)
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149+
/* Coprocessor 0 Usable */
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#define SR_CU0 (1 << 28)
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/* Coprocessor 1 Usable */
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#define SR_CU1 (1 << 29)
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/* Coprocessor 2 Usable */
154+
#define SR_CU2 (1 << 30)
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/* Coprocessor 3 Usable */
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#define SR_CU3 (1 << 31)
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158+
#ifdef __cplusplus
159+
}
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#endif
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162+
#endif /* _MIPSREGS_H */
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‎src/mips/hello/Makefile

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@@ -0,0 +1,17 @@
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TARGET = hello.psx
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TLOAD_ADDR = 0x80010000
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SRCS = \
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../common/hardware/cop0.s \
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crt0/crt0.s \
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main/main.c \
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LDSCRIPT = psx-exe.ld
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10+
## If "TLOAD_ADDR" was specified in the Makefile, pass it to the linker.
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ifneq ($(strip $(TLOAD_ADDR)),)
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LDFLAGS := -Wl,--defsym,TLOAD_ADDR=$(TLOAD_ADDR)
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else
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LDFLAGS =
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endif
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include ../common.mk

‎src/mips/hello/crt0/crt0.s

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/***************************************************************************
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* Copyright (C) 2019 PCSX-Redux authors *
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* *
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* This program is free software; you can redistribute it and/or modify *
5+
* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
11+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12+
* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
16+
* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#include <mipsregs.h>
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.set push
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.set noreorder
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.set noat
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.section .start, "ax", @progbits
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.align 2
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.global main
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.global _start
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.type _start, @function
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_start:
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la t0, __bss_start
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la t1, __bss_end
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addiu t1, t1, 3
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srl t1, t1, 2
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sll t1, t1, 2
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beq t0, t1, _zero_bss_done
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nop
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40+
_zero_bss:
41+
sw zero, 0(t0)
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addiu t0, t0, 4
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bne t0, t1, _zero_bss
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nop
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_zero_bss_done:
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/* la gp, _gp*/
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li a0, 0
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j main
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li a1, 0
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/*
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.end _start
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.data
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.bss
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*/
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.extern __bss_start
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.extern __bss_end
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.extern _gp
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/* int _main(int argc, const char **argv, const char **envp) */
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.extern main
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.set pop

‎src/mips/hello/main/main.c

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/***************************************************************************
2+
* Copyright (C) 2019 PCSX-Redux authors *
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* *
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* This program is free software; you can redistribute it and/or modify *
5+
* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
7+
* (at your option) any later version. *
8+
* *
9+
* This program is distributed in the hope that it will be useful, *
10+
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
11+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12+
* GNU General Public License for more details. *
13+
* *
14+
* You should have received a copy of the GNU General Public License *
15+
* along with this program; if not, write to the *
16+
* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
18+
***************************************************************************/
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#include "common/hardware/cop0.h"
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int main() {
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return 0;
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}

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