Skip to content

Commit bef33f0

Browse files
godunkogodunko
committed
Configure DMA in circular mode.
Refactor ADCx initialization to share code.
1 parent 958d9b8 commit bef33f0

File tree

2 files changed

+54
-219
lines changed

2 files changed

+54
-219
lines changed

‎source/configuration.adb‎

Lines changed: 51 additions & 216 deletions
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ is
9191

9292
procedure Enable_Timers is
9393
begin
94-
null;
94+
A0B.STM32G474.SVD.TIM.TIM15_Periph.CR1.CEN := True;
9595
-- A0B.STM32F401.SVD.TIM.TIM3_Periph.CR1.CEN := True;
9696
-- -- Timers are configured in master-slave mode, so enable of TIM3 will
9797
-- -- enable other timers too.
@@ -127,6 +127,10 @@ is
127127

128128
procedure Initialize_ADC2;
129129

130+
procedure Initialize_ADCx
131+
(ADC : in out A0B.STM32G474.SVD.ADC.ADC1_Peripheral);
132+
-- Shared initialization code of both ADC
133+
130134
procedure Initialize_ADC12_Clock;
131135
-- ADC12 clock
132136

@@ -202,164 +206,63 @@ is
202206
renames A0B.STM32G474.SVD.ADC.ADC1_Periph;
203207

204208
begin
205-
-- ADC interrupt enable register (ADC_IER)
206-
207-
declare
208-
Value : A0B.STM32G474.SVD.ADC.IER_Register := ADC.IER;
209-
210-
begin
211-
Value.ADRDYIE := False; -- 0: ADRDY interrupt disabled
212-
Value.EOSMPIE := False; -- 0: EOSMP interrupt disabled
213-
Value.EOCIE := False; -- 0: EOC interrupt disabled
214-
Value.EOSIE := False; -- 0: EOS interrupt disabled
215-
Value.OVRIE := False; -- 0: Overrun interrupt disabled
216-
Value.JEOCIE := False; -- 0: JEOC interrupt disabled
217-
Value.JEOSIE := False; -- 0: JEOS interrupt disabled
218-
Value.AWD1IE := False;
219-
-- 0: Analog watchdog 1 interrupt disabled
220-
Value.AWD2IE := False;
221-
-- 0: Analog watchdog 1 interrupt disabled
222-
Value.AWD3IE := False;
223-
-- 0: Analog watchdog 3 interrupt disabled
224-
Value.JQOVFIE := False;
225-
-- 0: Injected Context Queue Overflow interrupt disabled
226-
227-
ADC.IER := Value;
228-
end;
229-
230-
-- ADC control register (ADC_CR)
231-
232-
-- declare
233-
-- Value : A0B.STM32G474.SVD.ADC.CR_Register
234-
-- := A0B.STM32G474.SVD.ADC.ADC1_Periph.CR;
235-
--
236-
-- begin
237-
-- Value.ADEN := False; -- <>
238-
-- Value.ADDIS := False; -- <>
239-
-- -- Value.ADDIS := True; -- 1: Write 1 to disable the ADC
240-
-- Value.ADSTART := False; -- <>
241-
-- Value.JADSTART := False; -- <>
242-
-- Value.ADSTP := False; -- <>
243-
-- Value.JADSTP := False; -- <>
244-
-- Value.ADVREGEN := True; -- 1: ADC Voltage regulator enabled
245-
-- Value.DEEPPWD := False; -- 0: ADC not in Deep-power down
246-
-- Value.ADCALDIF := False; -- <>
247-
-- Value.ADCAL := False; -- <>
248-
--
249-
-- A0B.STM32G474.SVD.ADC.ADC1_Periph.CR := Value;
250-
-- end;
251-
252-
-- ADC configuration register (ADC_CFGR)
253-
254-
declare
255-
Value : A0B.STM32G474.SVD.ADC.CFGR_Register := ADC.CFGR;
256-
257-
begin
258-
Value.DMAEN := True; -- 1: DMA enabled
259-
Value.DMACFG := False; -- 0: DMA One Shot mode selected
260-
Value.RES := 2#00#; -- 00: 12-bit
261-
Value.EXTSEL := 2#01110#; -- adc_ext_trg14: tim15_trgo
262-
Value.EXTEN := 2#01#;
263-
-- 01: Hardware trigger detection on the rising edge
264-
-- -- 00: Hardware trigger detection disabled (conversions can be
265-
-- -- launched by software)
266-
Value.OVRMOD := False;
267-
-- 0: ADC_DR register is preserved with the old data when an
268-
-- overrun is detected.
269-
Value.CONT := False; -- 0: Single conversion mode
270-
Value.AUTDLY := False; -- 0: Auto-delayed conversion mode off
271-
Value.ALIGN := False; -- 0: Right alignment
272-
Value.DISCEN := False;
273-
-- 0: Discontinuous mode for regular channels disabled
274-
Value.DISCNUM := 0; -- <>
275-
Value.JDISCEN := False;
276-
-- 0: Discontinuous mode on injected channels disabled
277-
Value.JQM := False;
278-
-- 0: JSQR mode 0: The Queue is never empty and maintains the last
279-
-- written configuration into JSQR
280-
Value.AWD1SGL := False;
281-
-- 0: Analog watchdog 1 enabled on all channels
282-
Value.AWD1EN := False;
283-
-- 0: Analog watchdog 1 disabled on regular channels
284-
Value.JAWD1EN := False;
285-
-- 0: Analog watchdog 1 disabled on injected channels
286-
Value.JAUTO := False;
287-
-- 0: Automatic injected group conversion disabled
288-
Value.AWD1CH := 2#00000#; -- <>
289-
Value.JQDIS := True; -- 1: Injected Queue disabled
209+
Initialize_ADCx (ADC);
290210

291-
ADC.CFGR := Value;
292-
end;
293-
294-
-- ADC configuration register 2 (ADC_CFGR2)
211+
-- ADC regular sequence register 1 (ADC_SQR1)
295212

296213
declare
297-
Value : A0B.STM32G474.SVD.ADC.CFGR2_Register := ADC.CFGR2;
214+
Value : A0B.STM32G474.SVD.ADC.SQR1_Register := ADC.SQR1;
298215

299216
begin
300-
Value.ROVSE := False; -- 0: Regular Oversampling disabled
301-
Value.JOVSE := False; -- 0: Injected Oversampling disabled
302-
Value.OVSR := 2#000#; -- <>
303-
Value.OVSS := 2#0000#; -- <>
304-
Value.TROVS := False;
305-
-- 0: All oversampled conversions for a channel are done
306-
-- consecutively following a trigger
307-
Value.ROVSM := False;
308-
-- 0: Continued mode: When injected conversions are triggered,
309-
-- the oversampling is temporary stopped and continued after the
310-
-- injection sequence (oversampling buffer is maintained during
311-
-- injected sequence)
312-
Value.GCOMP := False; -- 0: Regular ADC operating mode
313-
Value.SWTRIG := False;
314-
-- 0: Software trigger starts the conversion for sampling time
315-
-- control trigger mode
316-
Value.BULB := False; -- 0: Bulb sampling mode disabled
317-
Value.SMPTRIG := False;
318-
-- 0: Sampling time control trigger mode disabled
217+
Value.L := 5; -- 6 conversions
218+
Value.SQ1 := ADC1_IN12;
219+
Value.SQ2 := ADC1_IN12;
220+
Value.SQ3 := ADC1_IN15;
221+
Value.SQ4 := ADC1_IN15;
319222

320-
ADC.CFGR2 := Value;
223+
ADC.SQR1 := Value;
321224
end;
322225

323-
-- ADC sample time register 1 (ADC_SMPR1)
226+
-- ADC regular sequence register 2 (ADC_SQR2)
324227

325228
declare
326-
Value : A0B.STM32G474.SVD.ADC.SMPR1_Register := ADC.SMPR1;
229+
Value : A0B.STM32G474.SVD.ADC.SQR2_Register := ADC.SQR2;
327230

328231
begin
329-
Value.SMPPLUS := False;
330-
-- 0: The sampling time remains set to 2.5 ADC clock cycles
331-
-- remains
332-
Value.SMP.Arr := (others => 2#001#); -- 000: 6.5 ADC clock cycles
232+
-- Value.SQ5 := ADC1_IN4;
233+
-- Value.SQ6 := ADC1_IN4;
234+
Value.SQ5 := ADC1_OPAMP1;
235+
Value.SQ6 := ADC1_OPAMP1;
333236

334-
ADC.SMPR1 := Value;
237+
ADC.SQR2 := Value;
335238
end;
239+
end Initialize_ADC1;
336240

337-
-- ADC sample time register 2 (ADC_SMPR2)
338-
339-
declare
340-
Value : A0B.STM32G474.SVD.ADC.SMPR2_Register := ADC.SMPR2;
341-
342-
begin
343-
Value.SMP.Arr := (others => 2#001#); -- 000: 6.5 ADC clock cycles
241+
---------------------
242+
-- Initialize_ADC2 --
243+
---------------------
344244

345-
ADC.SMPR2 := Value;
346-
end;
245+
procedure Initialize_ADC2 is
246+
ADC : A0B.STM32G474.SVD.ADC.ADC1_Peripheral
247+
renames A0B.STM32G474.SVD.ADC.ADC2_Periph;
347248

348-
-- ADC watchdog threshold register 1 (ADC_TR1)
349-
-- ADC watchdog threshold register 2 (ADC_TR2)
350-
-- ADC watchdog threshold register 3 (ADC_TR3)
249+
begin
250+
Initialize_ADCx (ADC);
351251

352252
-- ADC regular sequence register 1 (ADC_SQR1)
353253

354254
declare
355255
Value : A0B.STM32G474.SVD.ADC.SQR1_Register := ADC.SQR1;
356256

357257
begin
258+
-- Value.L := 2#0010#; -- 3 conversions
358259
Value.L := 5; -- 6 conversions
359-
Value.SQ1 := ADC1_IN12;
360-
Value.SQ2 := ADC1_IN12;
361-
Value.SQ3 := ADC1_IN15;
362-
Value.SQ4 := ADC1_IN15;
260+
Value.SQ1 := ADC2_IN17;
261+
Value.SQ2 := ADC2_IN17;
262+
Value.SQ3 := ADC2_IN4;
263+
Value.SQ4 := ADC2_IN4;
264+
-- Value.SQ3 := ADC2_OPAMP2;
265+
-- Value.SQ4 := ADC2_OPAMP2;
363266

364267
ADC.SQR1 := Value;
365268
end;
@@ -370,33 +273,21 @@ is
370273
Value : A0B.STM32G474.SVD.ADC.SQR2_Register := ADC.SQR2;
371274

372275
begin
373-
-- Value.SQ5 := ADC1_IN4;
374-
-- Value.SQ6 := ADC1_IN4;
375-
Value.SQ5 := ADC1_OPAMP1;
376-
Value.SQ6 := ADC1_OPAMP1;
276+
Value.SQ5 := ADC12_IN2;
277+
Value.SQ6 := ADC12_IN2;
278+
-- Value.SQ5 := ADC2_OPAMP3;
279+
-- Value.SQ6 := ADC2_OPAMP3;
377280

378281
ADC.SQR2 := Value;
379282
end;
380-
381-
-- ADC regular sequence register 3 (ADC_SQR3)
382-
-- ADC regular sequence register 4 (ADC_SQR4)
383-
-- ADC injected sequence register (ADC_JSQR)
384-
-- ADC offset y register (ADC_OFRy)
385-
-- ADC analog watchdog 2 configuration register (ADC_AWD2CR)
386-
-- ADC analog watchdog 3 configuration register (ADC_AWD3CR)
387-
-- ADC differential mode selection register (ADC_DIFSEL)
388-
-- ADC calibration factors (ADC_CALFACT)
389-
-- ADC Gain compensation Register (ADC_GCOMP)
390-
end Initialize_ADC1;
283+
end Initialize_ADC2;
391284

392285
---------------------
393-
-- Initialize_ADC2 --
286+
-- Initialize_ADCx --
394287
---------------------
395288

396-
procedure Initialize_ADC2 is
397-
ADC : A0B.STM32G474.SVD.ADC.ADC1_Peripheral
398-
renames A0B.STM32G474.SVD.ADC.ADC2_Periph;
399-
289+
procedure Initialize_ADCx
290+
(ADC : in out A0B.STM32G474.SVD.ADC.ADC1_Peripheral) is
400291
begin
401292
-- ADC interrupt enable register (ADC_IER)
402293

@@ -425,38 +316,20 @@ is
425316

426317
-- ADC control register (ADC_CR)
427318

428-
-- declare
429-
-- Value : A0B.STM32G474.SVD.ADC.CR_Register
430-
-- := A0B.STM32G474.SVD.ADC.ADC1_Periph.CR;
431-
--
432-
-- begin
433-
-- Value.ADEN := False; -- <>
434-
-- Value.ADDIS := False; -- <>
435-
-- -- Value.ADDIS := True; -- 1: Write 1 to disable the ADC
436-
-- Value.ADSTART := False; -- <>
437-
-- Value.JADSTART := False; -- <>
438-
-- Value.ADSTP := False; -- <>
439-
-- Value.JADSTP := False; -- <>
440-
-- Value.ADVREGEN := True; -- 1: ADC Voltage regulator enabled
441-
-- Value.DEEPPWD := False; -- 0: ADC not in Deep-power down
442-
-- Value.ADCALDIF := False; -- <>
443-
-- Value.ADCAL := False; -- <>
444-
--
445-
-- A0B.STM32G474.SVD.ADC.ADC1_Periph.CR := Value;
446-
-- end;
447-
448319
-- ADC configuration register (ADC_CFGR)
449320

450321
declare
451322
Value : A0B.STM32G474.SVD.ADC.CFGR_Register := ADC.CFGR;
452323

453324
begin
454325
Value.DMAEN := True; -- 1: DMA enabled
455-
Value.DMACFG := False; -- 0: DMA One Shot mode selected
326+
Value.DMACFG := True; -- 1: DMA Circular mode selected
456327
Value.RES := 2#00#; -- 00: 12-bit
457328
Value.EXTSEL := 2#01110#; -- adc_ext_trg14: tim15_trgo
458329
Value.EXTEN := 2#01#;
459330
-- 01: Hardware trigger detection on the rising edge
331+
-- -- 00: Hardware trigger detection disabled (conversions can be
332+
-- -- launched by software)
460333
Value.OVRMOD := False;
461334
-- 0: ADC_DR register is preserved with the old data when an
462335
-- overrun is detected.
@@ -542,39 +415,8 @@ is
542415
-- ADC watchdog threshold register 1 (ADC_TR1)
543416
-- ADC watchdog threshold register 2 (ADC_TR2)
544417
-- ADC watchdog threshold register 3 (ADC_TR3)
545-
546418
-- ADC regular sequence register 1 (ADC_SQR1)
547-
548-
declare
549-
Value : A0B.STM32G474.SVD.ADC.SQR1_Register := ADC.SQR1;
550-
551-
begin
552-
-- Value.L := 2#0010#; -- 3 conversions
553-
Value.L := 5; -- 6 conversions
554-
Value.SQ1 := ADC2_IN17;
555-
Value.SQ2 := ADC2_IN17;
556-
Value.SQ3 := ADC2_IN4;
557-
Value.SQ4 := ADC2_IN4;
558-
-- Value.SQ3 := ADC2_OPAMP2;
559-
-- Value.SQ4 := ADC2_OPAMP2;
560-
561-
ADC.SQR1 := Value;
562-
end;
563-
564419
-- ADC regular sequence register 2 (ADC_SQR2)
565-
566-
declare
567-
Value : A0B.STM32G474.SVD.ADC.SQR2_Register := ADC.SQR2;
568-
569-
begin
570-
Value.SQ5 := ADC12_IN2;
571-
Value.SQ6 := ADC12_IN2;
572-
-- Value.SQ5 := ADC2_OPAMP3;
573-
-- Value.SQ6 := ADC2_OPAMP3;
574-
575-
ADC.SQR2 := Value;
576-
end;
577-
578420
-- ADC regular sequence register 3 (ADC_SQR3)
579421
-- ADC regular sequence register 4 (ADC_SQR4)
580422
-- ADC injected sequence register (ADC_JSQR)
@@ -584,7 +426,7 @@ is
584426
-- ADC differential mode selection register (ADC_DIFSEL)
585427
-- ADC calibration factors (ADC_CALFACT)
586428
-- ADC Gain compensation Register (ADC_GCOMP)
587-
end Initialize_ADC2;
429+
end Initialize_ADCx;
588430

589431
----------------------------
590432
-- Initialize_ADC12_Clock --
@@ -632,9 +474,6 @@ is
632474
Value.VBATSEL := False;
633475
-- 0: VBAT channel disabled.
634476

635-
Value.VSENSESEL := True;
636-
Value.VBATSEL := True;
637-
638477
A0B.STM32G474.SVD.ADC.ADC12_Common_Periph.CCR := Value;
639478
end;
640479
end Initialize_ADC12_Common;
@@ -703,17 +542,15 @@ is
703542
Peripheral_Address => A0B.STM32G474.SVD.ADC.ADC1_Periph.DR'Address,
704543
Peripheral_Data_Size => A0B.STM32_DMA.Half_Word,
705544
Memory_Data_Size => A0B.STM32_DMA.Half_Word,
706-
Circular_Mode => False);
707-
-- Circular_Mode => True);
545+
Circular_Mode => True);
708546

709547
ADC2_DMA_CH.DMA_CH.Initialize;
710548
ADC2_DMA_CH.DMA_CH.Configure_Peripheral_To_Memory
711549
(Priority => A0B.STM32_DMA.Very_High,
712550
Peripheral_Address => A0B.STM32G474.SVD.ADC.ADC2_Periph.DR'Address,
713551
Peripheral_Data_Size => A0B.STM32_DMA.Half_Word,
714552
Memory_Data_Size => A0B.STM32_DMA.Half_Word,
715-
Circular_Mode => False);
716-
-- Circular_Mode => True);
553+
Circular_Mode => True);
717554
end Initialize_DMA;
718555

719556
---------------------
@@ -1733,8 +1570,6 @@ is
17331570
-- -- registers.
17341571
--
17351572
-- TIM.EGR.UG := True;
1736-
1737-
TIM.CR1.CEN := True;
17381573
end Initialize_TIM15;
17391574

17401575
--------------------

0 commit comments

Comments
 (0)