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4 | 4 | -- SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
5 | 5 | -- |
6 | 6 |
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| 7 | +with A0B.STM32F401.SVD.ADC; |
7 | 8 | with A0B.STM32F401.SVD.RCC; |
8 | 9 | with A0B.STM32F401.SVD.TIM; |
9 | 10 | with A0B.STM32F401.TIM_Lines; |
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21 | 22 |
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22 | 23 | procedure Initialize_GPIO; |
23 | 24 |
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| 25 | + procedure Initialize_ADC1; |
| 26 | + |
24 | 27 | procedure Initialize_TIM3; |
25 | 28 | -- Configure TIM3. Timer is disabled. It generates TRGO on CEN set. |
26 | 29 |
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52 | 55 | begin |
53 | 56 | Initialize_GPIO; |
54 | 57 | Initialize_UART; |
| 58 | + Initialize_ADC1; |
55 | 59 | Initialize_TIM3; |
56 | 60 | Initialize_TIM4; |
57 | 61 |
|
58 | 62 | Enable_Timers; |
59 | 63 | end Initialize; |
60 | 64 |
|
| 65 | + --------------------- |
| 66 | + -- Initialize_ADC1 -- |
| 67 | + --------------------- |
| 68 | + |
| 69 | + procedure Initialize_ADC1 is |
| 70 | + use A0B.STM32F401.SVD.ADC; |
| 71 | + |
| 72 | + begin |
| 73 | + A0B.STM32F401.SVD.RCC.RCC_Periph.APB2ENR.ADC1EN := True; |
| 74 | + |
| 75 | + -- Clear SR - Not needed |
| 76 | + |
| 77 | + -- Configure CR1 |
| 78 | + |
| 79 | + declare |
| 80 | + Aux : A0B.STM32F401.SVD.ADC.CR1_Register := ADC1_Periph.CR1; |
| 81 | + |
| 82 | + begin |
| 83 | + -- Aux.AWDCH := <>; -- Not used |
| 84 | + Aux.EOCIE := False; -- 0: EOC interrupt disabled |
| 85 | + Aux.AWDIE := False; -- 0: Analog watchdog interrupt disabled |
| 86 | + Aux.JEOCIE := False; -- 0: JEOC interrupt disabled |
| 87 | + Aux.SCAN := True; -- 1: Scan mode enabled |
| 88 | + -- Aux.AWDSGL := <>; -- Not used |
| 89 | + Aux.JAUTO := False; |
| 90 | + -- 0: Automatic injected group conversion disabled |
| 91 | + Aux.DISCEN := False; |
| 92 | + -- 0: Discontinuous mode on regular channels disabled |
| 93 | + Aux.JDISCEN := False; |
| 94 | + -- 0: Discontinuous mode on injected channels disabled |
| 95 | + -- Aux.DISCNUM := <>; -- Not used |
| 96 | + Aux.JAWDEN := False; |
| 97 | + -- 0: Analog watchdog disabled on injected channels |
| 98 | + Aux.AWDIE := False; |
| 99 | + -- 0: Analog watchdog disabled on regular channels |
| 100 | + Aux.RES := 2#00#; -- 00: 12-bit (15 ADCCLK cycles) |
| 101 | + Aux.OVRIE := False; -- 0: Overrun interrupt disabled |
| 102 | + |
| 103 | + ADC1_Periph.CR1 := Aux; |
| 104 | + end; |
| 105 | + |
| 106 | + -- Configure CR2 |
| 107 | + |
| 108 | + declare |
| 109 | + Aux : A0B.STM32F401.SVD.ADC.CR2_Register := ADC1_Periph.CR2; |
| 110 | + |
| 111 | + begin |
| 112 | + Aux.ADON := False; |
| 113 | + -- 0: Disable ADC conversion and go to power down mode |
| 114 | + Aux.CONT := False; -- 0: Single conversion mode |
| 115 | + Aux.DMA := False; -- 0: DMA mode disabled |
| 116 | + Aux.DDS := True; |
| 117 | + -- 1: DMA requests are issued as long as data are converted and DMA=1 |
| 118 | + Aux.EOCS := True; |
| 119 | + -- 1: The EOC bit is set at the end of each regular conversion. |
| 120 | + -- Overrun detection is enabled. |
| 121 | + Aux.ALIGN := False; -- 0: Right alignment |
| 122 | + -- Aux.JEXTSEL := <>; -- Not used |
| 123 | + Aux.JEXTEN := 2#00#; -- 00: Trigger detection disabled |
| 124 | + Aux.JSWSTART := False; -- 0: Reset state |
| 125 | + Aux.EXTSEL := 2#1010#; -- 1010: Timer 5 CC1 event |
| 126 | + Aux.EXTEN := 2#01#; -- 01: Trigger detection on the rising edge |
| 127 | + Aux.SWSTART := False; -- 0: Reset state |
| 128 | + |
| 129 | + ADC1_Periph.CR2 := Aux; |
| 130 | + end; |
| 131 | + |
| 132 | + -- Configure SMPR1 |
| 133 | + |
| 134 | + ADC1_Periph.SMPR1 := 0; -- 000: 3 cycles, for channels 10..18 |
| 135 | + |
| 136 | + -- Configure SMPR2 |
| 137 | + |
| 138 | + ADC1_Periph.SMPR2 := 0; -- 000: 3 cycles, for channels 0..9 |
| 139 | + |
| 140 | + -- Configure JOFR1 - Not used |
| 141 | + |
| 142 | + -- Configure JOFR2 - Not used |
| 143 | + |
| 144 | + -- Configure JOFR3 - Not used |
| 145 | + |
| 146 | + -- Configure JOFR4 - Not used |
| 147 | + |
| 148 | + -- Configure HTR - Not used |
| 149 | + |
| 150 | + -- Configure LTR - Not used |
| 151 | + |
| 152 | + -- Configure SQR1 |
| 153 | + |
| 154 | + declare |
| 155 | + Aux : A0B.STM32F401.SVD.ADC.SQR1_Register := ADC1_Periph.SQR1; |
| 156 | + |
| 157 | + begin |
| 158 | + -- Aux.SQ.Arr (16) := <>; -- Not used |
| 159 | + -- Aux.SQ.Arr (15) := <>; -- Not used |
| 160 | + -- Aux.SQ.Arr (14) := <>; -- Not used |
| 161 | + -- Aux.SQ.Arr (13) := <>; -- Not used |
| 162 | + Aux.L := 2#1000#; -- 1000: 9 conversions |
| 163 | + |
| 164 | + ADC1_Periph.SQR1 := Aux; |
| 165 | + end; |
| 166 | + |
| 167 | + -- Configure SQR2 |
| 168 | + |
| 169 | + declare |
| 170 | + Aux : A0B.STM32F401.SVD.ADC.SQR2_Register := ADC1_Periph.SQR2; |
| 171 | + |
| 172 | + begin |
| 173 | + -- Aux.SQ.Arr (12) := <>; -- Not used |
| 174 | + -- Aux.SQ.Arr (11) := <>; -- Not used |
| 175 | + -- Aux.SQ.Arr (10) := <>; -- Not used |
| 176 | + Aux.SQ.Arr (9) := 7; -- IN7 |
| 177 | + Aux.SQ.Arr (8) := 6; -- IN6 |
| 178 | + Aux.SQ.Arr (7) := 5; -- IN5 |
| 179 | + |
| 180 | + ADC1_Periph.SQR2 := Aux; |
| 181 | + end; |
| 182 | + |
| 183 | + -- Configure SQR3 |
| 184 | + |
| 185 | + declare |
| 186 | + Aux : A0B.STM32F401.SVD.ADC.SQR3_Register := ADC1_Periph.SQR3; |
| 187 | + |
| 188 | + begin |
| 189 | + Aux.SQ.Arr (6) := 4; -- IN4 |
| 190 | + Aux.SQ.Arr (5) := 3; -- IN3 |
| 191 | + Aux.SQ.Arr (4) := 2; -- IN2 |
| 192 | + Aux.SQ.Arr (3) := 1; -- IN1 |
| 193 | + Aux.SQ.Arr (2) := 0; -- IN0 |
| 194 | + Aux.SQ.Arr (1) := 17; -- IN17 VREFINT |
| 195 | + |
| 196 | + ADC1_Periph.SQR3 := Aux; |
| 197 | + end; |
| 198 | + |
| 199 | + -- Configure JSQR - Not used |
| 200 | + |
| 201 | + -- Configure CCR |
| 202 | + |
| 203 | + declare |
| 204 | + Aux : CCR_Register := ADC_Common_Periph.CCR; |
| 205 | + |
| 206 | + begin |
| 207 | + Aux.ADCPRE := 2#01#; -- PCLK2 divided by 4 |
| 208 | + Aux.VBATE := False; -- 0: VBAT channel disabled |
| 209 | + Aux.TSVREFE := True; |
| 210 | + -- 1: Temperature sensor and VREFINT channel enabled |
| 211 | + |
| 212 | + ADC_Common_Periph.CCR := Aux; |
| 213 | + end; |
| 214 | + |
| 215 | + -- Enable ADC |
| 216 | + |
| 217 | + ADC1_Periph.CR2.ADON := True; |
| 218 | + end Initialize_ADC1; |
| 219 | + |
61 | 220 | --------------------- |
62 | 221 | -- Initialize_GPIO -- |
63 | 222 | --------------------- |
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