Some fixes to the startup code - clocks configs (arduino#89)

* Reverted 1MHz clock generator to GCLK5 instead GCLK7
Fixed the clock divider of 1MHz clock generator to be 48 (its source is DFLL which clocking at 48MHz, so 48 / 48 = 1, it was 48 / 24 = 2).
Updated the PLLs to the proper Ratio afetr the change of the 1MHz clock source.
Disabled GCLK_GENCTRL_DIVSEL reg on the 12MHz clock generator, since this caused the clock to be 1.5MHz.

* Fixed a description comment.

Author: aryelevin

cores/arduino/startup.c

@@ -37,7 +37,7 @@
 //USE DPLL0 for 120MHZ
 #define MAIN_CLOCK_SOURCE				  GCLK_GENCTRL_SRC_DPLL0
 
-#define GENERIC_CLOCK_GENERATOR_1M		  (7u)
+#define GENERIC_CLOCK_GENERATOR_1M		  (5u)
 //#define CRYSTALLESS
 
 #else
@@ -97,7 +97,7 @@ void SystemInit( void )
   }
 
   /* ----------------------------------------------------------------------------------------------
-   * 3) Put Generic Clock Generator 3 as source for Generic Clock Gen 0 (DFLL48M reference)
+   * 3) Put OSCULP32K as source for Generic Clock Generator 0
    */
   GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
 
@@ -146,7 +146,7 @@ void SystemInit( void )
       /* Wait for synchronization */
     }
 
-  GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_1M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
+  GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_1M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(48u);
 
   while ( GCLK->SYNCBUSY.bit.GENCTRL5 ){
     /* Wait for synchronization */
@@ -158,9 +158,9 @@ void SystemInit( void )
   */
 
   //PLL0 is 120MHz
-  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK7_Val);
+  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
 
-  OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59); //120 Mhz
+  OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(119); //120 Mhz
 
   while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
 
@@ -172,9 +172,9 @@ void SystemInit( void )
   while( OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0 );
 
   //PLL1 is 100MHz
-  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK7_Val);
+  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
 
-  OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(49); //100 Mhz
+  OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(99); //100 Mhz
 
   while(OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.DPLLRATIO);
 
@@ -216,7 +216,7 @@ void SystemInit( void )
   GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_12M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
     GCLK_GENCTRL_IDC |
     GCLK_GENCTRL_DIV(4) |
-    GCLK_GENCTRL_DIVSEL |
+    //GCLK_GENCTRL_DIVSEL |
     //GCLK_GENCTRL_OE |
     GCLK_GENCTRL_GENEN;