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1 parent 8f9d419 commit f7c4fa6Copy full SHA for f7c4fa6
cpp/ql/lib/semmle/code/cpp/controlflow/Nullness.qll
@@ -46,7 +46,7 @@ predicate nullCheckExpr(Expr checkExpr, Variable var) {
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or
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exists(LogicalAndExpr op, AnalysedExpr child |
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expr = op and
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- (op.getLeftOperand() = child or op.getRightOperand() = child) and
+ op.getAnOperand() = child and
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nullCheckExpr(child, v)
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)
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@@ -99,7 +99,7 @@ predicate validCheckExpr(Expr checkExpr, Variable var) {
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validCheckExpr(child, v)
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