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I think there is perhaps a characteristic you are overlooking on the 1PPS signal. "...Hertz (Hz) is the standard unit of frequency, measuring the number of cycles or repetitions per second of a periodic phenomenon..." If you have a 1Hz/1PPS signal which is stable over a very long period of time, you are solving the "per-second" portion of the frequency measurement. From that, you can run a counter that increments every clock cycle, and then gate the counter's input with the 1Hz/PPS signal to sample how many cycles or repetitions occurred in your periodic phenomenon over that second. From that you may discover if your measured clock is faster or slower than your 1Hz/PPS reference, and if the clock source is steerable, it may be adjusted and compared with the reference source again. On your idea of reducing the time it takes to synchronize clocks - making a fast correction, or frequent correction would appear in the clock as a glitch or jitter (respectively). In situations where you have a clock feeding a Phase-Locked-Loop (PLL) multiplier or divider (which describes basically all electronic applications above 25-50MHz nowadays) - a glitch or introducing jitter to a clock could result in the PLL unlocking, and the dependent circuitry falling out of function (typically there is a state machine in logic which has a prerequisite that the PLL be stable before it presumes the logic will function correctly, thus blocking or resetting the operation of the logic). This is true even with the output of the F9T's frequency output - the logic of the ARM microcontroller inside the module runs at a given frequency, and its output is not precisely time-aligned to the second, it's the closest internal clock edge of the logic's frequency - the error between the sample time for the edge and the calculated truth of when the edge should have occurred is quantization. The F9T has a quantization error message (UBX-TIM-TP) that can output what the quantization error of the last edge was relative to the calculated solution, this can be used to feed forward into a delay line to correct the error out (but the delay line would need to delay for at least a second for that to be useful). This is similar to PTP's hardware stamping where a packet is output with a time, and the hardware can tell WHEN that packet was actually transmitted, and then append that information of its observation to the outbound packet. So about synchronizing clocks - we get a message that can't update any faster than one second telling us what time it is, and with a 1PPS signal when get a sharp edge of WHEN that message was true. That second's horizon IS the synchronization moment, and it reoccurs every second - anything tighter (IMO) is going to be buried in jitter. So the question then is - what application would you have that would need a synchronization event instance more than once every second (and would the synchronization actually destabilize your system? |
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I understand that the PPS reference effectively acts as an interrupt for the serial data, but modern GNSS SoCs have observation frequencies significantly higher than 1Hz now. Budget options can usually do 10Hz timing (+"PPS" set to 10Hz), and the Septentrios can do 100Hz observations, so in this case, would it be better to use a faster observation rate and a matching pulse? |
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I have been working on the hardware design side of GNSS systems for a few years now (mainly for positioning), and am now looking into designing some hardware for timing purposes as well.
One thing I noticed in many PTP projects is the use of 1PPS timing signal, presumably at the default output of 1Hz, even if the module in use (F9T, etc) can be configured for much higher frequencies (up to 25MHz for example). Wouldn't there be a benefit using a higher frequency clock sync in terms of reducing the time it takes to synchronize clocks or something else?
I would appreciate to know what others think about this.
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