Skip to content

Commit 71f6540

Browse files
JeffreyALawJeffreyALaw
committed
[PR target/115478] Accept ADD, IOR or XOR when combining objects with no bits in common
So the change to prefer ADD over IOR for combining two objects with no bits in common is (IMHO) generally good. It has some minor fallout. In particular the aarch64 port (and I suspect others) have patterns that recognize IOR, but not PLUS or XOR for these cases and thus tests which expected to optimize with IOR are no longer optimizing. Roger suggested using a code iterator for this purpose. Richard S. suggested a new match operator to cover those cases. I really like the match operator idea, but as Richard S. notes in the PR it would require either not validating the "no bits in common", which dramatically reduces the utility IMHO or we'd need some work to allow consistent results without polluting the nonzero bits cache. So this patch goes back to Roger's idea of just using a match iterator in the aarch64 backend (and presumably anywhere else we see this popping up). Bootstrapped and regression tested on aarch64-linux-gnu where it fixes bitint-args.c (as expected). PR target/115478 gcc/ * config/aarch64/iterators.md (any_or_plus): New code iterator. * config/aarch64/aarch64.md (extr<mode>5_insn): Use any_or_plus. (extr<mode>5_insn_alt, extrsi5_insn_uxtw): Likewise. (extrsi5_insn_uxtw_alt, extrsi5_insn_di): Likewise. gcc/testsuite/ * gcc.target/aarch64/bitint-args.c: Update expected output.
1 parent 556248d commit 71f6540

File tree

3 files changed

+33
-25
lines changed

3 files changed

+33
-25
lines changed

‎gcc/config/aarch64/aarch64.md

Lines changed: 27 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -6194,10 +6194,11 @@
61946194

61956195
(define_insn "*extr<mode>5_insn"
61966196
[(set (match_operand:GPI 0 "register_operand" "=r")
6197-
(ior:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
6198-
(match_operand 3 "const_int_operand" "n"))
6199-
(lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r")
6200-
(match_operand 4 "const_int_operand" "n"))))]
6197+
(any_or_plus:GPI
6198+
(ashift:GPI (match_operand:GPI 1 "register_operand" "r")
6199+
(match_operand 3 "const_int_operand" "n"))
6200+
(lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r")
6201+
(match_operand 4 "const_int_operand" "n"))))]
62016202
"UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
62026203
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
62036204
"extr\\t%<w>0, %<w>1, %<w>2, %4"
@@ -6208,10 +6209,11 @@
62086209
;; so we have to match both orderings.
62096210
(define_insn "*extr<mode>5_insn_alt"
62106211
[(set (match_operand:GPI 0 "register_operand" "=r")
6211-
(ior:GPI (lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r")
6212-
(match_operand 4 "const_int_operand" "n"))
6213-
(ashift:GPI (match_operand:GPI 1 "register_operand" "r")
6214-
(match_operand 3 "const_int_operand" "n"))))]
6212+
(any_or_plus:GPI
6213+
(lshiftrt:GPI (match_operand:GPI 2 "register_operand" "r")
6214+
(match_operand 4 "const_int_operand" "n"))
6215+
(ashift:GPI (match_operand:GPI 1 "register_operand" "r")
6216+
(match_operand 3 "const_int_operand" "n"))))]
62156217
"UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode)
62166218
&& (UINTVAL (operands[3]) + UINTVAL (operands[4])
62176219
== GET_MODE_BITSIZE (<MODE>mode))"
@@ -6223,10 +6225,11 @@
62236225
(define_insn "*extrsi5_insn_uxtw"
62246226
[(set (match_operand:DI 0 "register_operand" "=r")
62256227
(zero_extend:DI
6226-
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6227-
(match_operand 3 "const_int_operand" "n"))
6228-
(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6229-
(match_operand 4 "const_int_operand" "n")))))]
6228+
(any_or_plus:SI
6229+
(ashift:SI (match_operand:SI 1 "register_operand" "r")
6230+
(match_operand 3 "const_int_operand" "n"))
6231+
(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6232+
(match_operand 4 "const_int_operand" "n")))))]
62306233
"UINTVAL (operands[3]) < 32 &&
62316234
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
62326235
"extr\\t%w0, %w1, %w2, %4"
@@ -6236,10 +6239,11 @@
62366239
(define_insn "*extrsi5_insn_uxtw_alt"
62376240
[(set (match_operand:DI 0 "register_operand" "=r")
62386241
(zero_extend:DI
6239-
(ior:SI (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6240-
(match_operand 4 "const_int_operand" "n"))
6241-
(ashift:SI (match_operand:SI 1 "register_operand" "r")
6242-
(match_operand 3 "const_int_operand" "n")))))]
6242+
(any_or_plus:SI
6243+
(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6244+
(match_operand 4 "const_int_operand" "n"))
6245+
(ashift:SI (match_operand:SI 1 "register_operand" "r")
6246+
(match_operand 3 "const_int_operand" "n")))))]
62436247
"UINTVAL (operands[3]) < 32 &&
62446248
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
62456249
"extr\\t%w0, %w1, %w2, %4"
@@ -6248,13 +6252,13 @@
62486252

62496253
(define_insn "*extrsi5_insn_di"
62506254
[(set (match_operand:SI 0 "register_operand" "=r")
6251-
(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6252-
(match_operand 3 "const_int_operand" "n"))
6253-
(match_operator:SI 6 "subreg_lowpart_operator"
6254-
[(zero_extract:DI
6255-
(match_operand:DI 2 "register_operand" "r")
6256-
(match_operand 5 "const_int_operand" "n")
6257-
(match_operand 4 "const_int_operand" "n"))])))]
6255+
(any_or_plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6256+
(match_operand 3 "const_int_operand" "n"))
6257+
(match_operator:SI 6 "subreg_lowpart_operator"
6258+
[(zero_extract:DI
6259+
(match_operand:DI 2 "register_operand" "r")
6260+
(match_operand 5 "const_int_operand" "n")
6261+
(match_operand 4 "const_int_operand" "n"))])))]
62586262
"UINTVAL (operands[3]) < 32
62596263
&& UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32
62606264
&& INTVAL (operands[3]) == INTVAL (operands[5])"

‎gcc/config/aarch64/iterators.md

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2657,6 +2657,10 @@
26572657
;; Code iterator for logical operations
26582658
(define_code_iterator LOGICAL [and ior xor])
26592659

2660+
;; Code iterator for operations that are equivalent when the
2661+
;; two input operands are known have disjoint bits set.
2662+
(define_code_iterator any_or_plus [plus ior xor])
2663+
26602664
;; LOGICAL with plus, for when | gets converted to +.
26612665
(define_code_iterator LOGICAL_OR_PLUS [and ior xor plus])
26622666

‎gcc/testsuite/gcc.target/aarch64/bitint-args.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ CHECK_ARG(65)
6969
** f65:
7070
** extr (x[0-9]+), x3, x2, 1
7171
** and (x[0-9]+), x2, 1
72-
** orr (x[0-9]+), \2, \1, lsl 1
72+
** add (x[0-9]+), \2, \1, lsl 1
7373
** asr (x[0-9]+), \1, 63
7474
** stp \3, \4, \[x0\]
7575
** ret
@@ -80,7 +80,7 @@ CHECK_ARG(127)
8080
** f127:
8181
** extr (x[0-9]+), x3, x2, 63
8282
** and (x[0-9]+), x2, 9223372036854775807
83-
** orr (x[0-9]+), \2, \1, lsl 63
83+
** add (x[0-9]+), \2, \1, lsl 63
8484
** asr (x[0-9]+), \1, 1
8585
** stp \3, \4, \[x0\]
8686
** ret

0 commit comments

Comments
 (0)