Bitstream Design Kit - Draft

[ganeshgore]

It will be great to have a some framework to design custom bitstreams.
following snippet of code presents some API ideas that might help in designing a custom bitstream.

fpga_bdk = load_bdk(fabric_indenpendent_bitstream,
                    general_switchbox_directory,
                    vpr_architecture_file,
                    openfpga_architecture_file)

fpga_bdk.get_modules()   # List all the unique modules in the design
fpga_bdk.get_instances()  # Get all configurable instances in all the module
fpga_bdk.reset_all()     # Resets all the bit in the current fabric
fpga_bdk.set_default()   # Sets all bits to default setting

cbx11 = fpga_bdk.get_instance("cbx_1__1_")

# This will list all the bitstream segments in the current instance
cbx11.list_bit_segemets()
cbx11.type                # This returns routing or pb_type keyword

# If routing module (CB and SBs)
# List all the outputs/drivers of the current routing block "<side>_<indx>"
cbx11.outputs()
cbx11.inputs()            # List all the inputs of the current routing block "<side>_<indx>"
# List all the inputs connected to the given output pins
cbx11.get_output("<output_pin>").inputs()
# List all the outputs connected to the given input pins
cbx11.get_output("<input_pins>").outputs()
# Sets the bitstream segment value for the current module
cbx11.get_output("<output_pin>").select_input("<input_pin>")

# If Physical blocks
clb = fpga_bdk.get_instance("grid_clb_1__1_")
clb.type  # pb_type

clb.list_connection()       # lists collection of crossbars/local_routing in the pb_type
clb.list_blocks()           # lists collection of blocks in side the pb_type


# Cross bar configuration
# list outputs to the crossbar "<block>_<indx>_<pin>_<indx>"
clb.get_connection("").outputs()
crobbbar_out = clb.get_connection("").get_output("<block>_<indx>_<pin>_<indx>")
crobbbar_out.inputs()  # list inputs to the given output crossbar pin
crobbbar_out.select_input("Input Pin Name")


# PB_type configuration
clb.list_blocks().