[proposed Label] Question

[josefoelias]

Hi,
I am trying to get your code work with my VHDL project (AXI MASTER), but I'm not familiar with Verilog.
I'm working in Vivado on school project and I need validate that my IP core works before I am testing it on HW.

I need one AXI slave (with memory if its possible) and test write read with my core.

If I understand it, I need to generate BFM with Phyton and then declare+instantiate it in my vhdl. But which files I need to generate ?

Thanks, Josef

[funningboy]

Hi,
uvm_axi is a quickly basic AXI protocol checker which is following the UVM standard flow contains( driver, sequencer, monitor, scoreboard). it's a good start point to know what's UVM and how to use it "http://www.testbench.in/UT_00_INDEX.html".
by default, we use run.py as Makefile to setup our test env, all uvm tests must be registered to run.py