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Add all generated STM32F2xx generic variant files
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
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‎variants/STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx/PeripheralPins.c

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‎variants/STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx/PinNamesVar.h

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/* Alternate pin name */
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PA_0_ALT1 = PA_0 | ALT1,
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PA_0_ALT2 = PA_0 | ALT2,
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PA_1_ALT1 = PA_1 | ALT1,
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PA_1_ALT2 = PA_1 | ALT2,
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PA_2_ALT1 = PA_2 | ALT1,
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PA_2_ALT2 = PA_2 | ALT2,
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PA_3_ALT1 = PA_3 | ALT1,
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PA_3_ALT2 = PA_3 | ALT2,
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PA_4_ALT1 = PA_4 | ALT1,
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PA_5_ALT1 = PA_5 | ALT1,
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PA_6_ALT1 = PA_6 | ALT1,
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PA_7_ALT1 = PA_7 | ALT1,
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PA_7_ALT2 = PA_7 | ALT2,
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PA_7_ALT3 = PA_7 | ALT3,
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PA_15_ALT1 = PA_15 | ALT1,
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PB_0_ALT1 = PB_0 | ALT1,
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PB_0_ALT2 = PB_0 | ALT2,
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PB_1_ALT1 = PB_1 | ALT1,
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PB_1_ALT2 = PB_1 | ALT2,
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PB_3_ALT1 = PB_3 | ALT1,
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PB_4_ALT1 = PB_4 | ALT1,
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PB_5_ALT1 = PB_5 | ALT1,
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PB_8_ALT1 = PB_8 | ALT1,
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PB_9_ALT1 = PB_9 | ALT1,
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PB_14_ALT1 = PB_14 | ALT1,
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PB_14_ALT2 = PB_14 | ALT2,
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PB_15_ALT1 = PB_15 | ALT1,
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PB_15_ALT2 = PB_15 | ALT2,
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PC_0_ALT1 = PC_0 | ALT1,
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PC_0_ALT2 = PC_0 | ALT2,
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PC_1_ALT1 = PC_1 | ALT1,
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PC_1_ALT2 = PC_1 | ALT2,
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PC_2_ALT1 = PC_2 | ALT1,
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PC_2_ALT2 = PC_2 | ALT2,
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PC_3_ALT1 = PC_3 | ALT1,
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PC_3_ALT2 = PC_3 | ALT2,
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PC_4_ALT1 = PC_4 | ALT1,
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PC_5_ALT1 = PC_5 | ALT1,
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PC_6_ALT1 = PC_6 | ALT1,
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PC_7_ALT1 = PC_7 | ALT1,
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PC_8_ALT1 = PC_8 | ALT1,
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PC_9_ALT1 = PC_9 | ALT1,
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PC_10_ALT1 = PC_10 | ALT1,
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PC_11_ALT1 = PC_11 | ALT1,
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/* SYS_WKUP */
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#ifdef PWR_WAKEUP_PIN1
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SYS_WKUP1 = PA_0,
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#endif
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#ifdef PWR_WAKEUP_PIN2
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SYS_WKUP2 = NC,
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#endif
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#ifdef PWR_WAKEUP_PIN3
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SYS_WKUP3 = NC,
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#endif
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#ifdef PWR_WAKEUP_PIN4
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SYS_WKUP4 = NC,
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#endif
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#ifdef PWR_WAKEUP_PIN5
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SYS_WKUP5 = NC,
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#endif
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#ifdef PWR_WAKEUP_PIN6
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SYS_WKUP6 = NC,
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#endif
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#ifdef PWR_WAKEUP_PIN7
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SYS_WKUP7 = NC,
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#endif
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#ifdef PWR_WAKEUP_PIN8
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SYS_WKUP8 = NC,
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#endif
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/* USB */
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#ifdef USBCON
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USB_OTG_FS_DM = PA_11,
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USB_OTG_FS_DP = PA_12,
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USB_OTG_FS_ID = PA_10,
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USB_OTG_FS_SOF = PA_8,
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USB_OTG_FS_VBUS = PA_9,
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USB_OTG_HS_DM = PB_14,
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USB_OTG_HS_DP = PB_15,
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USB_OTG_HS_ID = PB_12,
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USB_OTG_HS_SOF = PA_4,
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USB_OTG_HS_ULPI_CK = PA_5,
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USB_OTG_HS_ULPI_D0 = PA_3,
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USB_OTG_HS_ULPI_D1 = PB_0,
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USB_OTG_HS_ULPI_D2 = PB_1,
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USB_OTG_HS_ULPI_D3 = PB_10,
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USB_OTG_HS_ULPI_D4 = PB_11,
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USB_OTG_HS_ULPI_D5 = PB_12,
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USB_OTG_HS_ULPI_D6 = PB_13,
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USB_OTG_HS_ULPI_D7 = PB_5,
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USB_OTG_HS_ULPI_DIR = PC_2,
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USB_OTG_HS_ULPI_NXT = PC_3,
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USB_OTG_HS_ULPI_STP = PC_0,
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USB_OTG_HS_VBUS = PB_13,
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#endif

‎variants/STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx/boards_entry.txt

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# This file help to add generic board entry.
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# upload.maximum_size and product_line have to be verified
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# and changed if needed.
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# See: https://github.com/stm32duino/wiki/wiki/Add-a-new-variant-%28board%29
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# Generic F205RBTx
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GenF2.menu.pnum.GENERIC_F205RBTX=Generic F205RBTx
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GenF2.menu.pnum.GENERIC_F205RBTX.upload.maximum_size=131072
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GenF2.menu.pnum.GENERIC_F205RBTX.upload.maximum_data_size=65536
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GenF2.menu.pnum.GENERIC_F205RBTX.build.board=GENERIC_F205RBTX
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GenF2.menu.pnum.GENERIC_F205RBTX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RBTX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205RCTx
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GenF2.menu.pnum.GENERIC_F205RCTX=Generic F205RCTx
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GenF2.menu.pnum.GENERIC_F205RCTX.upload.maximum_size=262144
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GenF2.menu.pnum.GENERIC_F205RCTX.upload.maximum_data_size=65536
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GenF2.menu.pnum.GENERIC_F205RCTX.build.board=GENERIC_F205RCTX
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GenF2.menu.pnum.GENERIC_F205RCTX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RCTX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205RETx
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GenF2.menu.pnum.GENERIC_F205RETX=Generic F205RETx
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GenF2.menu.pnum.GENERIC_F205RETX.upload.maximum_size=524288
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GenF2.menu.pnum.GENERIC_F205RETX.upload.maximum_data_size=65536
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GenF2.menu.pnum.GENERIC_F205RETX.build.board=GENERIC_F205RETX
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GenF2.menu.pnum.GENERIC_F205RETX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RETX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205RFTx
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GenF2.menu.pnum.GENERIC_F205RFTX=Generic F205RFTx
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GenF2.menu.pnum.GENERIC_F205RFTX.upload.maximum_size=786432
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GenF2.menu.pnum.GENERIC_F205RFTX.upload.maximum_data_size=65536
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GenF2.menu.pnum.GENERIC_F205RFTX.build.board=GENERIC_F205RFTX
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GenF2.menu.pnum.GENERIC_F205RFTX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RFTX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205RGTx
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GenF2.menu.pnum.GENERIC_F205RGTX=Generic F205RGTx
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GenF2.menu.pnum.GENERIC_F205RGTX.upload.maximum_size=1048576
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GenF2.menu.pnum.GENERIC_F205RGTX.upload.maximum_data_size=65536
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GenF2.menu.pnum.GENERIC_F205RGTX.build.board=GENERIC_F205RGTX
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GenF2.menu.pnum.GENERIC_F205RGTX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RGTX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205REYx
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GenF2.menu.pnum.GENERIC_F205REYX=Generic F205REYx
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GenF2.menu.pnum.GENERIC_F205REYX.upload.maximum_size=524288
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GenF2.menu.pnum.GENERIC_F205REYX.upload.maximum_data_size=131072
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GenF2.menu.pnum.GENERIC_F205REYX.build.board=GENERIC_F205REYX
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GenF2.menu.pnum.GENERIC_F205REYX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205REYX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205RGYx
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GenF2.menu.pnum.GENERIC_F205RGYX=Generic F205RGYx
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GenF2.menu.pnum.GENERIC_F205RGYX.upload.maximum_size=1048576
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GenF2.menu.pnum.GENERIC_F205RGYX.upload.maximum_data_size=131072
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GenF2.menu.pnum.GENERIC_F205RGYX.build.board=GENERIC_F205RGYX
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GenF2.menu.pnum.GENERIC_F205RGYX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RGYX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F205RGEx
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GenF2.menu.pnum.GENERIC_F205RGEX=Generic F205RGEx
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GenF2.menu.pnum.GENERIC_F205RGEX.upload.maximum_size=1048576
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GenF2.menu.pnum.GENERIC_F205RGEX.upload.maximum_data_size=131072
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GenF2.menu.pnum.GENERIC_F205RGEX.build.board=GENERIC_F205RGEX
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GenF2.menu.pnum.GENERIC_F205RGEX.build.product_line=STM32F205xx
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GenF2.menu.pnum.GENERIC_F205RGEX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F215RETx
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GenF2.menu.pnum.GENERIC_F215RETX=Generic F215RETx
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GenF2.menu.pnum.GENERIC_F215RETX.upload.maximum_size=524288
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GenF2.menu.pnum.GENERIC_F215RETX.upload.maximum_data_size=131072
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GenF2.menu.pnum.GENERIC_F215RETX.build.board=GENERIC_F215RETX
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GenF2.menu.pnum.GENERIC_F215RETX.build.product_line=STM32F215xx
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GenF2.menu.pnum.GENERIC_F215RETX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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# Generic F215RGTx
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GenF2.menu.pnum.GENERIC_F215RGTX=Generic F215RGTx
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GenF2.menu.pnum.GENERIC_F215RGTX.upload.maximum_size=1048576
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GenF2.menu.pnum.GENERIC_F215RGTX.upload.maximum_data_size=131072
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GenF2.menu.pnum.GENERIC_F215RGTX.build.board=GENERIC_F215RGTX
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GenF2.menu.pnum.GENERIC_F215RGTX.build.product_line=STM32F215xx
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GenF2.menu.pnum.GENERIC_F215RGTX.build.variant=STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx
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‎variants/STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx/generic_clock.c

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/*
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*******************************************************************************
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* Copyright (c) 2020-2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_GENERIC_F205RBTX) || defined(ARDUINO_GENERIC_F205RCTX) ||\
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defined(ARDUINO_GENERIC_F205RETX) || defined(ARDUINO_GENERIC_F205REYX) ||\
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defined(ARDUINO_GENERIC_F205RFTX) || defined(ARDUINO_GENERIC_F205RGEX) ||\
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defined(ARDUINO_GENERIC_F205RGTX) || defined(ARDUINO_GENERIC_F205RGYX) ||\
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defined(ARDUINO_GENERIC_F215RETX) || defined(ARDUINO_GENERIC_F215RGTX)
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#include "pins_arduino.h"
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/**
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* @brief System Clock Configuration
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* @param None
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* @retval None
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*/
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WEAK void SystemClock_Config(void)
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{
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/* SystemClock_Config can be generated by STM32CubeMX */
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#warning "SystemClock_Config() is empty. Default clock at reset is used."
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}
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#endif /* ARDUINO_GENERIC_* */

‎variants/STM32F2xx/F205R(B-C-E-F-G)Tx_F205R(E-G)Yx_F205RGEx_F215R(E-G)Tx/variant.cpp

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/*
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*******************************************************************************
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* Copyright (c) 2020-2021, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_GENERIC_F205RBTX) || defined(ARDUINO_GENERIC_F205RCTX) ||\
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defined(ARDUINO_GENERIC_F205RETX) || defined(ARDUINO_GENERIC_F205REYX) ||\
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defined(ARDUINO_GENERIC_F205RFTX) || defined(ARDUINO_GENERIC_F205RGEX) ||\
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defined(ARDUINO_GENERIC_F205RGTX) || defined(ARDUINO_GENERIC_F205RGYX) ||\
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defined(ARDUINO_GENERIC_F215RETX) || defined(ARDUINO_GENERIC_F215RGTX)
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#include "pins_arduino.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Digital PinName array
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const PinName digitalPin[] = {
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PA_0,
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PA_1,
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PA_2,
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PA_3,
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PA_4,
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PA_5,
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PA_6,
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PA_7,
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PA_8,
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PA_9,
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PA_10,
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PA_11,
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PA_12,
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PA_13,
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PA_14,
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PA_15,
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PB_0,
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PB_1,
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PB_2,
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PB_3,
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PB_4,
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PB_5,
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PB_6,
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PB_7,
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PB_8,
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PB_9,
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PB_10,
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PB_11,
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PB_12,
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PB_13,
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PB_14,
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PB_15,
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PC_0,
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PC_1,
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PC_2,
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PC_3,
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PC_4,
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PC_5,
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PC_6,
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PC_7,
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PC_8,
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PC_9,
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PC_10,
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PC_11,
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PC_12,
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PC_13,
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PC_14,
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PC_15,
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PD_2,
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PH_0,
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PH_1
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};
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// Analog (Ax) pin number array
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const uint32_t analogInputPin[] = {
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0, // A0, PA0
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1, // A1, PA1
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2, // A2, PA2
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3, // A3, PA3
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4, // A4, PA4
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5, // A5, PA5
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6, // A6, PA6
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7, // A7, PA7
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16, // A8, PB0
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17, // A9, PB1
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32, // A10, PC0
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33, // A11, PC1
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34, // A12, PC2
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35, // A13, PC3
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36, // A14, PC4
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37 // A15, PC5
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};
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif /* ARDUINO_GENERIC_* */

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