test: new MSR baselines

pb8o · zulinx86 · commit e050c601efa2 · 2023-08-11T10:23:15.000+01:00
Due to the new guest kernel versions, the MSRs seen by the guest are different. The only difference is MSR_IA32_SPEC_CTRL[1], which passes IBRS information in bit 0 now. [1]: https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html Signed-off-by: Pablo Barbáchano <pablob@amazon.com>
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_4.14host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_4.14host_4.14guest.csv
@@ -10,7 +10,7 @@ MSR_ADDR,VALUE
 0x2c,0x1000000
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_4.14host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_4.14host_5.10guest.csv
@@ -10,7 +10,7 @@ MSR_ADDR,VALUE
 0x2c,0x1000000
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_4.14guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_4.14guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_4.14host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_4.14host_4.14guest.csv
@@ -10,7 +10,7 @@ MSR_ADDR,VALUE
 0x2c,0x1000000
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_4.14host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_4.14host_5.10guest.csv
@@ -10,7 +10,7 @@ MSR_ADDR,VALUE
 0x2c,0x1000000
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_5.10host_4.14guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_5.10host_5.10guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_6.1host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_6.1host_4.14guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_6.1host_5.10guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_4.14host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_4.14host_4.14guest.csv
@@ -10,7 +10,7 @@ MSR_ADDR,VALUE
 0x2c,0x1000000
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_4.14host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_4.14host_5.10guest.csv
@@ -10,7 +10,7 @@ MSR_ADDR,VALUE
 0x2c,0x1000000
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_4.14guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_5.10guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_4.14guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_4.14guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x0
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_5.10guest.csv
@@ -11,7 +11,7 @@ MSR_ADDR,VALUE
 0x34,0x0
 0x3a,0x1
 0x3b,0x0
-0x48,0x0
+0x48,0x1
 0x8b,0x100000000
 0xc1,0x0
 0xc2,0x0
