fix(vmm): Changes T2A not to unset MMX and FXSR bits

The MMX bit (CPUID.80000001h:EDX[23]) and the FXSR bit
(CPUID.80000001h:EDX[24]) are unset on Intel CPUs as they are
reserved in Intel specification. However, as described in AMD APM, these
bits are same as CPUID.01h:EDX[23] and CPUID.01h:EDX[24] respectively.
These bits are set to 1 on T2 instance, Intel Skylake, Intel Cascade
Lake, Intel Ice Lake and AMD Milan. Thus, T2A template does not need to
unset CPUID.80000001h:EDX[23,24].

Signed-off-by: Takahiro Itazuri <itazur@amazon.com>

Author: zulinx86

CHANGELOG.md

@@ -41,6 +41,8 @@
 - Fixed the T2A CPU template to disable SVM (nested virtualization).
 - Fixed the T2A CPU template to set EferLmsleUnsupported bit
   (CPUID.80000008h:EBX[20]), which indicates that EFER[LMSLE] is not supported.
+- Fixed the T2A CPU template not to unset the MMX bit (CPUID.80000001h:EDX[23])
+  and the FXSR bit (CPUID.80000001h:EDX[24]).
 
 ## [1.3.0]
 

resources/tests/static_cpu_templates/t2a.json

@@ -71,7 +71,7 @@
         },
         {
           "register": "edx",
-          "bitmap": "0bxxxxx00000xxxxxxxxxxxxxxxxxxxxxx"
+          "bitmap": "0bxxxxx00xx0xxxxxxxxxxxxxxxxxxxxxx"
         }
       ]
     },

src/vmm/src/cpu_config/x86_64/static_cpu_templates/t2a.rs

@@ -208,14 +208,12 @@ pub fn t2a() -> CustomCpuTemplate {
                     },
                     // EDX:
                     // - Bit 22: MmxExt (AMD APM) / Reserved (Intel SDM)
-                    // - Bit 23: MMX (AMD APM) / Reserved (Intel SDM)
-                    // - Bit 24: FSXR (AMD APM) / Reserved (Intel SDM)
                     // - Bit 25: FFXSR (AMD APM) / Reserved (Intel SDM)
                     // - Bit 26: Page1GB (AMD APM) / 1-GByte pages (Intel SDM)
                     CpuidRegisterModifier {
                         register: CpuidRegister::Edx,
                         bitmap: RegisterValueFilter {
-                            filter: 0b0000_0111_1100_0000_0000_0000_0000_0000,
+                            filter: 0b0000_0110_0100_0000_0000_0000_0000_0000,
                             value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
                         },
                     },

tests/integration_tests/functional/test_feat_parity.py

@@ -125,8 +125,6 @@ def test_feat_parity_cpuid_inst_set(vm):
         ),
         (0x80000001, 0x0, "edx",
             (1 << 22) | # MmxExt
-            (1 << 23) | # MMX
-            (1 << 24) | # FXSR
             (1 << 25) # FFXSR
         ),
         (0x80000008, 0x0, "ebx",