PyTorch Pool1d + Squeeze + io_stream + Catapult failure

[sei-jgwohlbier]

Prerequisites

Please make sure to check off these prerequisites before submitting a bug report.

• Test that the bug appears on the current version of the master branch. Make sure to include the commit hash of the commit you checked out.
• Check that the issue hasn't already been reported, by checking the currently open issues.
• If there are steps to reproduce the problem, make sure to write them down below.
• If relevant, please include the hls4ml project files, which were created directly before and/or after the bug.

Quick summary

PyTorch Pool1d + Squeeze + io_stream + Catapult fails to compile

Details

Running the test case below using Pool1d, squeeze, io_stream, and Catapult backend fails with error shown.

Steps to Reproduce

Add what needs to be done to reproduce the bug. Add commented code examples and make sure to include the original model files / code, and the commit hash you are working on.

1. Clone the hls4ml repository
2. Checkout the master branch, with commit hash: [71bf4ae]
3. Run conversion on code below.

from pathlib import Path

import numpy as np
import os
import pprint
import shutil
import torch
import torch.nn as nn
from torchinfo import summary

from hls4ml.converters import convert_from_pytorch_model
from hls4ml.utils.config import config_from_pytorch_model

test_root_path = Path(__file__).parent

if __name__ == "__main__":

    class test(nn.Module):
        def __init__(self, size_in, momentum=0.2):
            super().__init__()
            self.avgpool = nn.AvgPool1d(size_in)
            self.relu = nn.ReLU()

        def forward(self, x):
            z = self.avgpool(x)
            z = torch.squeeze(z)
            z = self.relu(z)
            return z

    n_in = 2
    n_out = 1
    size_in = 4
    n_batch = 3

    X_input_shape = (n_batch, n_in, size_in)

    model = test(size_in)

    io_type="io_stream"
    backend="Catapult"
    #backend="Vivado"
    output_dir = str(test_root_path / f"hls4mlprj_pool_squeeze_{backend}_io_stream")

    if os.path.exists(output_dir):
        print("delete project dir")
        shutil.rmtree(output_dir)
    if os.path.isfile(output_dir + ".tar.gz"):
        print("delete tar.gz")
        os.remove(output_dir + ".tar.gz")

    model.eval()
    print(model)
    summary(model, input_size=X_input_shape)

    X_input = np.random.rand(*X_input_shape)

    with torch.no_grad():
        pytorch_prediction = model(torch.Tensor(X_input))

    # X_input_hls is channels last
    X_input_hls = np.ascontiguousarray(X_input.transpose(0, 2, 1))

    # write tb data
    ipf = "./tb_input_features.dat"
    if os.path.isfile(ipf):
        os.remove(ipf)
    with open(ipf, "ab") as f:
        for x in X_input_hls:
            np.savetxt(f, x.flatten()[None]) # None trick for one line per

    opf = "./tb_output_predictions.dat"
    if os.path.isfile(opf):
        os.remove(opf)
    with open(opf, "ab") as f:
        for p in pytorch_prediction:
            np.savetxt(f, p.flatten()[None])

    default_precision="ap_fixed<16,6,AP_TRN_ZERO,AP_SAT_SYM>"
    default_precision="ap_fixed<32,12>"
    config = config_from_pytorch_model(model,
                                       input_shape=X_input_shape[-2:],
                                       backend=backend,
                                       channels_last_conversion="internal",
                                       default_precision=default_precision,
                                       granularity="name",
                                       transpose_outputs=False)
    config["Model"]["Strategy"] = "Resource"
    config["Model"]["BramFactor"] = 0

    pprint.pprint(config)

    hls_model = convert_from_pytorch_model(
        model,
        output_dir=output_dir,
        input_data_tb=ipf,
        output_data_tb=opf,
        backend=backend,
        hls_config=config,
        io_type=io_type,
    )

    hls_model.compile()

Expected behavior

Successful synthesis.

Actual behavior

Output:

delete project dir
delete tar.gz
test(
  (avgpool): AvgPool1d(kernel_size=(4,), stride=(4,), padding=(0,))
  (relu): ReLU()
)
==========================================================================================
Layer (type:depth-idx)                   Output Shape              Param #
==========================================================================================
test                                     [3, 2]                    --
├─AvgPool1d: 1-1                         [3, 2, 1]                 --
├─ReLU: 1-2                              [3, 2]                    --
==========================================================================================
Total params: 0
Trainable params: 0
Non-trainable params: 0
Total mult-adds (M): 0
==========================================================================================
Input size (MB): 0.00
Forward/backward pass size (MB): 0.00
Params size (MB): 0.00
Estimated Total Size (MB): 0.00
==========================================================================================
{'InputShape': (2, 4),
 'LayerName': {'avgpool': {'ConvImplementation': 'LineBuffer',
                           'Precision': {'accum': 'auto', 'result': 'auto'},
                           'ReuseFactor': 1,
                           'Trace': False},
               'relu': {'Precision': {'result': 'auto',
                                      'table': 'fixed<18,8,TRN,WRAP,0>'},
                        'ReuseFactor': 1,
                        'TableSize': 1024,
                        'Trace': False},
               'squeeze': {'Precision': {'result': 'auto'}, 'Trace': False},
               'x': {'Precision': {'result': 'auto'}, 'Trace': False}},
 'Model': {'BramFactor': 0,
           'ChannelsLastConversion': 'internal',
           'Precision': {'default': 'ap_fixed<32,12>'},
           'ReuseFactor': 1,
           'Strategy': 'Resource',
           'TraceOutput': False,
           'TransposeOutputs': False},
 'PytorchModel': test(
  (avgpool): AvgPool1d(kernel_size=(4,), stride=(4,), padding=(0,))
  (relu): ReLU()
)}
Interpreting Model ...
Topology:
Layer name: avgpool, layer type: AveragePooling1D, input shape: [[None, 2, 4]]
Layer name: squeeze, layer type: Reshape, input shape: [[None, 2, 1]]
Layer name: relu, layer type: Activation, input shape: [[None, 2]]
Writing HLS project
Copying NNET files to local firmware directory
... copying AC ac_types headers from /home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/writer/../templates/catapult/ac_types/
... copying AC ac_math headers from /home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/writer/../templates/catapult/ac_math/
... copying AC ac_simutils headers from /home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/writer/../templates/catapult/ac_simutils/
Done
Traceback (most recent call last):
  File "/home/asicflow-user/work/ece-18-725/ResNet/python/test_pool_squeeze.py", line 102, in <module>
    hls_model.compile()
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/model/graph.py", line 801, in compile
    self._compile()
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/model/graph.py", line 820, in _compile
    self._top_function_lib = ctypes.cdll.LoadLibrary(lib_name)
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/ctypes/__init__.py", line 452, in LoadLibrary
    return self._dlltype(name)
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/ctypes/__init__.py", line 374, in __init__
    self._handle = _dlopen(self._name, mode)
OSError: /home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/firmware/myproject-72b5179b.so: cannot open shared object file: No such file or directory

Trying to run build_lib.sh shows the compilation error:

./build_lib.sh 
firmware/myproject.cpp: In function 'void myproject(ac_channel<nnet::array<ac_fixed<32, 12, true>, 2> >&, ac_channel<nnet::array<ac_fixed<32, 12, true>, 2> >&)':
firmware/myproject.cpp:43:53: error: cannot convert 'ac_channel<nnet::array<ac_fixed<32, 12, true>, 2> >' to 'nnet::array<ac_fixed<32, 12, true>, 2>*'
   43 |     nnet::transpose_2d<layer2_t, layer5_t, config5>(layer2_out, layer5_out); // transpose_input_for_squeeze
      |                                                     ^~~~~~~~~~
      |                                                     |
      |                                                     ac_channel<nnet::array<ac_fixed<32, 12, true>, 2> >
In file included from firmware/parameters.h:12,
                 from firmware/myproject.cpp:4:
firmware/nnet_utils/nnet_array.h:16:26: note:   initializing argument 1 of 'void nnet::transpose_2d(data_T*, res_T*) [with data_T = nnet::array<ac_fixed<32, 12, true>, 2>; res_T = nnet::array<ac_fixed<32, 12, true>, 1>; CONFIG_T = config5]'
   16 | void transpose_2d(data_T data[CONFIG_T::height * CONFIG_T::width], res_T data_t[CONFIG_T::height * CONFIG_T::width]) {
      |                   ~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
firmware/nnet_utils/nnet_array.h: In instantiation of 'void nnet::transpose_2d(data_T*, res_T*) [with data_T = nnet::array<ac_fixed<32, 12, true>, 2>; res_T = nnet::array<ac_fixed<32, 12, true>, 1>; CONFIG_T = config5]':
firmware/myproject.cpp:43:75:   required from here
firmware/nnet_utils/nnet_array.h:21:46: error: no match for 'operator=' (operand types are 'nnet::array<ac_fixed<32, 12, true>, 1>' and 'nnet::array<ac_fixed<32, 12, true>, 2>')
   21 |             data_t[j * CONFIG_T::height + i] = data[i * CONFIG_T::width + j];
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~
In file included from firmware/defines.h:4,
                 from firmware/myproject.h:8,
                 from firmware/myproject.cpp:3:
firmware/nnet_utils/nnet_types.h:21:12: note: candidate: 'nnet::array<T, N>& nnet::array<T, N>::operator=(const nnet::array<T, N>&) [with T = ac_fixed<32, 12, true>; unsigned int N = 1]'
   21 |     array &operator=(const array &other) {
      |            ^~~~~~~~
firmware/nnet_utils/nnet_types.h:21:35: note:   no known conversion for argument 1 from 'nnet::array<ac_fixed<32, 12, true>, 2>' to 'const nnet::array<ac_fixed<32, 12, true>, 1>&'
   21 |     array &operator=(const array &other) {
      |                      ~~~~~~~~~~~~~^~~~~
g++: error: myproject.o: No such file or directory

Optional

Possible fix

N/A

Additional context

Related bug: #1054

[vloncar]

Unfortunately, if you use channels_first, we need to do internal transpose and this was not implemented for streaming io in Catapult backend

[sei-jgwohlbier]

So to do io_stream and Catapult with PyTorch I will have to make my PyTorch model native channels last and then set channels_last_conversion="off" in the call to config_from_pytorch_model?

[vloncar]

It can still be channels first during training and conversion, just be sure to transpose your inputs before passing them to the model predict and later the firmware

[sei-jgwohlbier]

Hmmm. That's what I was doing, I thought.

This seems very relevant. In this commit line 100 has "internal". But the next commit to this file changed it to "off". I'm still using "internal". Perhaps @JanFSchulte can shed light on why that changed and whether it still should work for me with io_stream and Catapult.

When I run a complete example, with the check above reverted to "internal", then the synthesis almost goes all the way through but fails with the error below.

Complete example

from pathlib import Path

import numpy as np
import os
import pprint
import shutil
import torch
import torch.nn as nn
from torchinfo import summary

from hls4ml.converters import convert_from_pytorch_model
from hls4ml.utils.config import config_from_pytorch_model

test_root_path = Path(__file__).parent

if __name__ == "__main__":

    class test(nn.Module):
        def __init__(self, size_in, momentum=0.2):
            super().__init__()
            self.avgpool = nn.AvgPool1d(size_in)
            self.relu = nn.ReLU()

        def forward(self, x):
            z = self.avgpool(x)
            z = torch.squeeze(z)
            z = self.relu(z)
            return z

    n_in = 2
    n_out = 1
    size_in = 4
    n_batch = 3

    X_input_shape = (n_batch, n_in, size_in)

    model = test(size_in)

    io_type="io_stream"
    backend="Catapult"
    #backend="Vivado"
    output_dir = str(test_root_path / f"hls4mlprj_pool_squeeze_{backend}_io_stream")

    if os.path.exists(output_dir):
        print("delete project dir")
        shutil.rmtree(output_dir)
    if os.path.isfile(output_dir + ".tar.gz"):
        print("delete tar.gz")
        os.remove(output_dir + ".tar.gz")

    model.eval()
    print(model)
    summary(model, input_size=X_input_shape)

    X_input = np.random.rand(*X_input_shape)

    with torch.no_grad():
        pytorch_prediction = model(torch.Tensor(X_input))

    # X_input_hls is channels last
    X_input_hls = np.ascontiguousarray(X_input.transpose(0, 2, 1))

    # write tb data
    ipf = "./tb_input_features.dat"
    if os.path.isfile(ipf):
        os.remove(ipf)
    with open(ipf, "ab") as f:
        for x in X_input_hls:
            np.savetxt(f, x.flatten()[None]) # None trick for one line per

    opf = "./tb_output_predictions.dat"
    if os.path.isfile(opf):
        os.remove(opf)
    with open(opf, "ab") as f:
        for p in pytorch_prediction:
            np.savetxt(f, p.flatten()[None])

    default_precision="ap_fixed<16,6,AP_TRN_ZERO,AP_SAT_SYM>"
    default_precision="ap_fixed<32,12>"
    config = config_from_pytorch_model(model,
                                       input_shape=X_input_shape[-2:],
                                       backend=backend,
                                       channels_last_conversion="internal",
                                       default_precision=default_precision,
                                       granularity="name",
                                       transpose_outputs=False)
    config["Model"]["Strategy"] = "Resource"
    config["Model"]["BramFactor"] = 0

    pprint.pprint(config)

    hls_model = convert_from_pytorch_model(
        model,
        output_dir=output_dir,
        input_data_tb=ipf,
        output_data_tb=opf,
        backend=backend,
        hls_config=config,
        io_type=io_type,
    )

    hls_model.compile()

    print("pytorch_prediction")
    print(pytorch_prediction)

    # reshape hls prediction to channels last, then transpose
    hls_prediction = hls_model.predict(X_input_hls)

    print("hls_prediction")
    print(hls_prediction)

    rtol = 1.0e-5
    atol = 5.0e-2
    for p, h in zip(pytorch_prediction, hls_prediction):
        np.testing.assert_allclose(p,
                                   h,
                                   rtol=rtol, atol=atol)
        
    hls_model.build(csim=True, synth=True, cosim=True, validation=True)

Error:

python test_pool_squeeze.py 
delete project dir
delete tar.gz
test(
  (avgpool): AvgPool1d(kernel_size=(4,), stride=(4,), padding=(0,))
  (relu): ReLU()
)
==========================================================================================
Layer (type:depth-idx)                   Output Shape              Param #
==========================================================================================
test                                     [3, 2]                    --
├─AvgPool1d: 1-1                         [3, 2, 1]                 --
├─ReLU: 1-2                              [3, 2]                    --
==========================================================================================
Total params: 0
Trainable params: 0
Non-trainable params: 0
Total mult-adds (M): 0
==========================================================================================
Input size (MB): 0.00
Forward/backward pass size (MB): 0.00
Params size (MB): 0.00
Estimated Total Size (MB): 0.00
==========================================================================================
{'InputShape': (2, 4),
 'LayerName': {'avgpool': {'ConvImplementation': 'LineBuffer',
                           'Precision': {'accum': 'auto', 'result': 'auto'},
                           'ReuseFactor': 1,
                           'Trace': False},
               'relu': {'Precision': {'result': 'auto',
                                      'table': 'fixed<18,8,TRN,WRAP,0>'},
                        'ReuseFactor': 1,
                        'TableSize': 1024,
                        'Trace': False},
               'squeeze': {'Precision': {'result': 'auto'}, 'Trace': False},
               'x': {'Precision': {'result': 'auto'}, 'Trace': False}},
 'Model': {'BramFactor': 0,
           'ChannelsLastConversion': 'internal',
           'Precision': {'default': 'ap_fixed<32,12>'},
           'ReuseFactor': 1,
           'Strategy': 'Resource',
           'TraceOutput': False,
           'TransposeOutputs': False},
 'PytorchModel': test(
  (avgpool): AvgPool1d(kernel_size=(4,), stride=(4,), padding=(0,))
  (relu): ReLU()
)}
Interpreting Model ...
Topology:
Layer name: avgpool, layer type: AveragePooling1D, input shape: [[None, 2, 4]]
Layer name: squeeze, layer type: Reshape, input shape: [[None, 2, 1]]
Layer name: relu, layer type: Activation, input shape: [[None, 2]]
Writing HLS project
Copying NNET files to local firmware directory
... copying AC ac_types headers from /home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/writer/../templates/catapult/ac_types/
... copying AC ac_math headers from /home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/writer/../templates/catapult/ac_math/
... copying AC ac_simutils headers from /home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/writer/../templates/catapult/ac_simutils/
Done
pytorch_prediction
tensor([[0.5887, 0.1033],
        [0.4879, 0.5922],
        [0.7353, 0.4395]])
hls_prediction
[[0.58867073 0.10333633]
 [0.48792648 0.59219551]
 [0.73534298 0.4394598 ]]
catapult -product ultra -shell -f build_prj.tcl -eval 'set ::argv "reset=False csim=True synth=True cosim=True validation=True export=False vsynth=False fifo_opt=False bitfile=False ran_frame=5 sw_opt=False power=False da=False vhdl=False verilog=True bup=False"'
//  Catapult Ultra Synthesis 2024.2_2/1156857 (Production Release) Tue Jan 14 16:38:07 PST 2025
//  
//          Copyright (c) Siemens EDA, 1996-2025, All Rights Reserved.
//                        UNPUBLISHED, LICENSED SOFTWARE.
//             CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
//                   PROPERTY OF SIEMENS EDA OR ITS LICENSORS.
//  
//  Running on Linux asicflow-user@3cdef9654642:16751 3.10.0-1160.108.1.el7.x86_64 x86_64 aol
//  
//  Package information: SIFLIBS v27.2_2.0, HLS_PKGS v27.2_2.0, 
//                       SIF_TOOLKITS v27.2_2.0, SIF_XILINX v27.2_2.0, 
//                       SIF_ALTERA v27.2_2.0, CCS_LIBS v27.2_2.0, 
//                       CDS_PPRO v2024.1_3, CDS_DesignChecker v2024.2_1, 
//                       CDS_OASYS v21.1_3.1, CDS_PSR v24.1_0.20, 
//                       DesignPad v2.78_1.0, DesignAnalyzer 2024.2/1130210
//  
# Connected to license server /afs/ece.cmu.edu/support/mgc/share/image/usr/local/mgc/license.dat (LIC-13)
# Catapult product license successfully checked out, elapsed time 00:03 (LIC-14)
dofile ./build_prj.tcl
# > array set opt {
# >   reset      0
# >   csim       0
# >   synth      1
# >   cosim      0
# >   validation 0
# >   vhdl       1
# >   verilog    1
# >   export     0
# >   vsynth     0
# >   bitfile    0
# >   fifo_opt   0
# >   ran_frame  2
# >   sw_opt     0
# >   power      0
# >   da         0
# >   bup        0
# > }
# > set sfd [file dirname [info script]]
# .
# > if { [info exists ::argv] } {
# >   foreach arg $::argv {
# >     foreach {optname optval} [split $arg '='] {}
# >     if { [info exists opt($optname)] } {
# >       if {[string is integer -strict $optval]} {
# >         set opt($optname) $optval
# >       } else {
# >         set opt($optname) [string is true -strict $optval]
# >       }
# >     }
# >   }
# > }
# > puts "***** INVOKE OPTIONS *****"
# ***** INVOKE OPTIONS *****
# > foreach x [lsort [array names opt]] {
# >   puts "[format {   %-20s %s} $x $opt($x)]"
# > }
#    bitfile              0
#    bup                  0
#    cosim                1
#    csim                 1
#    da                   0
#    export               0
#    fifo_opt             0
#    power                0
#    ran_frame            5
#    reset                0
#    sw_opt               0
#    synth                1
#    validation           1
#    verilog              1
#    vhdl                 0
#    vsynth               0
# > puts ""
# 
# > proc report_time { op_name time_start time_end } {
# >   set time_taken [expr $time_end - $time_start]
# >   set time_s [expr ($time_taken / 1000) % 60]
# >   set time_m [expr ($time_taken / (1000*60)) % 60]
# >   set time_h [expr ($time_taken / (1000*60*60)) % 24]
# >   puts "***** ${op_name} COMPLETED IN ${time_h}h${time_m}m${time_s}s *****"
# > }
# > proc setup_xilinx_part { part } {
# >   set part_sav $part
# >   set libname [lindex [library get /CONFIG/PARAMETERS/Vivado/PARAMETERS/Xilinx/PARAMETERS/*/PARAMETERS/*/PARAMETERS/$part/LIBRARIES/*/NAME -match glob -ret v] 0]
# >   puts "Library Name: $libname"
# >   if { [llength $libname] == 1 } {
# >     set libpath [library get /CONFIG/PARAMETERS/Vivado/PARAMETERS/Xilinx/PARAMETERS/*/PARAMETERS/*/PARAMETERS/$part/LIBRARIES/*/NAME -match glob -ret p]
# >     puts "Library Path: $libpath"
# >     if { [regexp {/CONFIG/PARAMETERS/(\S+)/PARAMETERS/(\S+)/PARAMETERS/(\S+)/PARAMETERS/(\S+)/PARAMETERS/(\S+)/.*} $libpath dummy rtltool vendor family speed part] } {
# >       solution library add $libname -- -rtlsyntool $rtltool -vendor $vendor -family $family -speed $speed -part $part_sav
# >     } else {
# >       solution library add $libname -- -rtlsyntool Vivado
# >     }
# >   } else {
# >     logfile message "Could not find specific Xilinx base library for part '$part'. Using KINTEX-u\n" warning
# >     solution library add mgc_Xilinx-KINTEX-u-2_beh -- -rtlsyntool Vivado -manufacturer Xilinx -family KINTEX-u -speed -2 -part xcku115-flvb2104-2-i
# >   }
# >   solution library add Xilinx_RAMS
# >   solution library add Xilinx_ROMS
# >   solution library add Xilinx_FIFO
# > }
# > proc setup_asic_libs { args } {
# >   set do_saed 0
# >   foreach lib $args {
# >     solution library add $lib -- -rtlsyntool DesignCompiler
# >     if { [lsearch -exact {saed32hvt_tt0p78v125c_beh saed32lvt_tt0p78v125c_beh saed32rvt_tt0p78v125c_beh} $lib] != -1 } {
# >       set do_saed 1
# >     }
# >   }
# >   solution library add ccs_sample_mem
# >   solution library add ccs_sample_rom
# >   solution library add hls4ml_lib
# >   go libraries
# > 
# >   if { $do_saed } {
# >     source [application get /SYSTEM/ENV_MGC_HOME]/pkgs/siflibs/saed/setup_saedlib.tcl
# >   }
# > }
# > options set Input/CppStandard {c++17}
# c++17
# > options set Input/CompilerFlags -DRANDOM_FRAMES=$opt(ran_frame)
# -DRANDOM_FRAMES=5
# > options set Input/SearchPath {$MGC_HOME/shared/include/nnet_utils} -append
# {$MGC_HOME/shared/include/nnet_utils}
# > options set ComponentLibs/SearchPath {$MGC_HOME/shared/pkgs/ccs_hls4ml} -append
# {$MGC_HOME/pkgs/siflibs} {$MGC_HOME/shared/include/calypto_mem} {$MGC_HOME/pkgs/siflibs/nangate} {$MGC_HOME/pkgs/siflibs/saed} {$MGC_HOME/pkgs/siflibs/dware} {$MGC_HOME/pkgs/ccs_altera} {$MGC_HOME/pkgs/ccs_xilinx} {$MGC_HOME/pkgs/ccs_achronix} {$MGC_HOME/pkgs/siflibs/origami} {$MGC_HOME/pkgs/siflibs/microsemi} {$MGC_HOME/pkgs/ccs_lattice} {$MGC_HOME/pkgs/ccs_nx} {$MGC_HOME/pkgs/ccs_libs/interfaces/amba} {$MGC_HOME/pkgs/siflibs/ccs_fpga} {$MGC_HOME/shared/pkgs/ccs_hls4ml}
# > if {$opt(reset)} {
# >   project load myproject_prj.ccs
# >   go new
# > } else {
# >   project new -name myproject_prj
# > }
# > options set Message/ErrorOverride HIER-10 -remove
# ASM-11 ASM-48 ASM-63 ASM-69 ASSERT-1 CIN-8 CIN-17 CIN-46 CIN-48 CIN-49 CIN-50 CIN-54 CIN-84 CIN-87 CIN-109 CIN-110 CIN-111 CIN-112 CIN-188 CIN-214 CIN-243 CIN-244 CLUSTER-3 CNS-9 CRAAS-21 DIR-24 DIR-32 HIER-2 HIER-20 HIER-45 IFSYN-6 INCR-13 INCR-14 INCR-15 LIB-194 LIB-204 LIB-211 LIB-224 LOOP-21 MEM-65 MEM-78 MEM-82 MEM-83 MEM-88 MGEN-16 NL-21 NL-26 NL-30 NL-35 OPT-25 READ-8 READ-9 SCHD-37 SCHD-54 SCHD-55 SIF-6 SIF-17 SIF-20
# > solution options set Message/ErrorOverride HIER-10 -remove
# ASM-11 ASM-48 ASM-63 ASM-69 ASSERT-1 CIN-8 CIN-17 CIN-46 CIN-48 CIN-49 CIN-50 CIN-54 CIN-84 CIN-87 CIN-109 CIN-110 CIN-111 CIN-112 CIN-188 CIN-214 CIN-243 CIN-244 CLUSTER-3 CNS-9 CRAAS-21 DIR-24 DIR-32 HIER-2 HIER-20 HIER-45 IFSYN-6 INCR-13 INCR-14 INCR-15 LIB-194 LIB-204 LIB-211 LIB-224 LOOP-21 MEM-65 MEM-78 MEM-82 MEM-83 MEM-88 MGEN-16 NL-21 NL-26 NL-30 NL-35 OPT-25 READ-8 READ-9 SCHD-37 SCHD-54 SCHD-55 SIF-6 SIF-17 SIF-20
# > if {$opt(vhdl)}    {
# >   options set Output/OutputVHDL true
# > } else {
# >   options set Output/OutputVHDL false
# > }
# false
# > if {$opt(verilog)} {
# >   options set Output/OutputVerilog true
# > } else {
# >   options set Output/OutputVerilog false
# > }
# true
# > if { [info exists ::env(XILINX_PCL_CACHE)] } {
# > options set /Flows/Vivado/PCL_CACHE $::env(XILINX_PCL_CACHE)
# > solution options set /Flows/Vivado/PCL_CACHE $::env(XILINX_PCL_CACHE)
# > }
# > catch {flow package require /HLS4ML}
# 0
# > flow package require /SCVerify
# 10.4
# > flow package option set /SCVerify/INVOKE_ARGS "$sfd/firmware/weights $sfd/tb_data/./tb_input_features.dat $sfd/tb_data/./tb_output_predictions.dat"
# ./firmware/weights ./tb_data/./tb_input_features.dat ./tb_data/./tb_output_predictions.dat
# > set design_top myproject
# myproject
# > solution file add $sfd/firmware/myproject.cpp
# /INPUTFILES/1
# > solution file add $sfd/myproject_test.cpp -exclude true
# /INPUTFILES/2
# > set IOType io_stream
# io_stream
# > if { ![file exists $sfd/firmware/parameters.h] } {
# >   logfile message "Could not locate firmware/parameters.h. Unable to determine network configuration.\n" warning
# > } else {
# >   set pf [open "$sfd/firmware/parameters.h" "r"]
# >   while {![eof $pf]} {
# >     gets $pf line
# >     if { [string match {*io_type = nnet::io_stream*} $line] } {
# >       set IOType io_stream
# >       break
# >     }
# >   }
# >   close $pf
# > }
# > if { $IOType == "io_stream" } {
# > solution options set Architectural/DefaultRegisterThreshold 2050
# > }
# 2050
# > directive set -RESET_CLEARS_ALL_REGS no
# /RESET_CLEARS_ALL_REGS no
# > directive set -MEM_MAP_THRESHOLD [expr 2048 * 16 + 1]
# /MEM_MAP_THRESHOLD 32769
# > set hls_clock_period 5
# 5
# > go analyze
# Info: Starting transformation 'analyze' on solution 'solution.v1' (SOL-8)
# Creating project directory '/home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/myproject_prj/'. (PRJ-1)
# Moving session transcript to file "/home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/catapult.log"
# Front End called with arguments: -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include/nnet_utils -- /home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/firmware/myproject.cpp (CIN-69)
# Edison Design Group C++/C Front End - Version 6.6 (CIN-1)
# $MGC_HOME/shared/include/ac_std_float.h(192): Pragma 'hls_design<>' detected on routine 'ac::fx_div<8>' (CIN-6)
# $PROJECT_HOME/firmware/myproject.cpp(8): Pragma 'hls_design<top>' detected on routine 'myproject' (CIN-6)
# Source file analysis completed (CIN-68)
# Info: Completed transformation 'analyze' on solution 'solution.v1': elapsed time 10.07 seconds, memory usage 1367304kB, peak memory usage 1367304kB (SOL-9)
# > if { ! $opt(bup) } {
# > 
# > go compile
# > 
# > if {$opt(csim)} {
# >   puts "***** C SIMULATION *****"
# >   set time_start [clock clicks -milliseconds]
# >   flow run /SCVerify/launch_make ./scverify/Verify_orig_cxx_osci.mk {} SIMTOOL=osci sim
# >   set time_end [clock clicks -milliseconds]
# >   report_time "C SIMULATION" $time_start $time_end
# > }
# > 
# > puts "***** SETTING TECHNOLOGY LIBRARIES *****"
# > setup_xilinx_part {xcku115-flvb2104-2-i}
# > 
# > directive set -CLOCKS [list clk [list -CLOCK_PERIOD $hls_clock_period -CLOCK_EDGE rising -CLOCK_OFFSET 0.000000 -CLOCK_UNCERTAINTY 0.0 -RESET_KIND sync -RESET_SYNC_NAME rst -RESET_SYNC_ACTIVE high -RESET_ASYNC_NAME arst_n -RESET_ASYNC_ACTIVE low -ENABLE_NAME {} -ENABLE_ACTIVE high]]
# > 
# > if {$opt(synth)} {
# >   puts "***** C/RTL SYNTHESIS *****"
# >   set time_start [clock clicks -milliseconds]
# > 
# >   go assembly
# > 
# >   go architect
# > 
# >   go allocate
# > 
# >   go schedule
# > 
# >   go extract
# >   set time_end [clock clicks -milliseconds]
# >   report_time "C/RTL SYNTHESIS" $time_start $time_end
# > }
# > 
# > } else {
# >   go analyze
# > 
# >   directive set -CLOCKS [list clk [list -CLOCK_PERIOD $hls_clock_period -CLOCK_EDGE rising -CLOCK_OFFSET 0.000000 -CLOCK_UNCERTAINTY 0.0 -RESET_KIND sync -RESET_SYNC_NAME rst -RESET_SYNC_ACTIVE high -RESET_ASYNC_NAME arst_n -RESET_ASYNC_ACTIVE low -ENABLE_NAME {} -ENABLE_ACTIVE high]]
# > 
# >   set blocks [solution get /HIERCONFIG/USER_HBS/*/RESOLVED_NAME -match glob -rec 1 -ret v -state analyze]
# >   set bu_mappings {}
# >   set top [lindex $blocks 0]
# >   foreach block [lreverse [lrange $blocks 1 end]] {
# >     if { [string match {nnet::*} $block] == 0 } { continue }
# >     go analyze
# >     solution design set $block -top
# >     go compile
# >     solution library remove *
# >     puts "***** SETTING TECHNOLOGY LIBRARIES *****"
# > setup_xilinx_part {xcku115-flvb2104-2-i}
# >     go extract
# >     set block_soln "[solution get /TOP/name -checkpath 0].[solution get /VERSION -checkpath 0]"
# >     lappend bu_mappings [solution get /CAT_DIR] /$top/$block "\[Block\] $block_soln"
# >   }
# > 
# >   go analyze
# >   solution design set $top -top
# >   go compile
# > 
# >   if {$opt(csim)} {
# >     puts "***** C SIMULATION *****"
# >     set time_start [clock clicks -milliseconds]
# >     flow run /SCVerify/launch_make ./scverify/Verify_orig_cxx_osci.mk {} SIMTOOL=osci sim
# >     set time_end [clock clicks -milliseconds]
# >     report_time "C SIMULATION" $time_start $time_end
# >   }
# >   foreach {d i l} $bu_mappings {
# >     logfile message "solution options set ComponentLibs/SearchPath $d -append\n" info
# >     solution options set ComponentLibs/SearchPath $d -append
# >   }
# > 
# >   puts "***** SETTING TECHNOLOGY LIBRARIES *****"
# >   solution library remove *
# > setup_xilinx_part {xcku115-flvb2104-2-i}
# >   go compile
# >   foreach {d i l} $bu_mappings {
# >     logfile message "solution library add [list $l]\n" info
# >     eval solution library add [list $l]
# >   }
# >   go libraries
# > 
# >   foreach {d i l} $bu_mappings {
# >     set cnt [directive get $i/* -match glob -checkpath 0 -ret p]
# >     if { $cnt != {} } {
# >       logfile message "directive set $i -MAP_TO_MODULE [list $l]\n" info
# >       eval directive set $i -MAP_TO_MODULE [list $l]
# >     }
# >   }
# >   go assembly
# >   set design [solution get -name]
# >   logfile message "Adjusting FIFO_DEPTH for top-level interconnect channels\n" warning
# >   foreach ch_fifo_m2m [directive get -match glob -checkpath 0 -ret p $design/*_out:cns/MAP_TO_MODULE] {
# >     set ch_fifo [join [lrange [split $ch_fifo_m2m '/'] 0 end-1] /]/FIFO_DEPTH
# >     logfile message "directive set -match glob $ch_fifo 1\n" info
# >     directive set -match glob "$ch_fifo" 1
# >   }
# >   foreach ch_fifo_m2m [directive get -match glob -checkpath 0 -ret p $design/*_cpy*:cns/MAP_TO_MODULE] {
# >     set ch_fifo [join [lrange [split $ch_fifo_m2m '/'] 0 end-1] /]/FIFO_DEPTH
# >     logfile message "Bypass FIFO '$ch_fifo' depth set to 1 - larger value may be required to prevent deadlock\n" warning
# >     logfile message "directive set -match glob $ch_fifo 1\n" info
# >     directive set -match glob "$ch_fifo" 1
# >   }
# >   go architect
# >   go allocate
# >   go schedule
# >   go dpfsm
# >   go extract
# > }
# Info: Starting transformation 'compile' on solution 'myproject.v1' (SOL-8)
# Generating synthesis internal form... (CIN-3)
# $MGC_HOME/shared/include/ac_std_float.h(196): Found design routine 'ac::fx_div<8>' specified by directive (CIN-52)
# $PROJECT_HOME/firmware/myproject.cpp(12): Found top design routine 'myproject' specified by directive (CIN-52)
# $PROJECT_HOME/firmware/myproject.cpp(12): Synthesizing routine 'myproject' (CIN-13)
# $PROJECT_HOME/firmware/myproject.cpp(12): Inlining routine 'myproject' (CIN-14)
# $PROJECT_HOME/firmware/myproject.cpp(11): Pragma 'hls_resource<layer4_out:rsc>' detected, variable = 'layer4_out', module = 'ccs_ioport.ccs_out_wait' (CIN-341)
# $PROJECT_HOME/firmware/myproject.cpp(11): Pragma 'hls_resource<layer4_out:rsc>' detected, variables = 'layer4_out', module = 'ccs_ioport.ccs_out_wait' (CIN-9)
# $PROJECT_HOME/firmware/myproject.cpp(10): Pragma 'hls_resource<x:rsc>' detected, variable = 'x', module = 'ccs_ioport.ccs_in_wait' (CIN-341)
# $PROJECT_HOME/firmware/myproject.cpp(10): Pragma 'hls_resource<x:rsc>' detected, variables = 'x', module = 'ccs_ioport.ccs_in_wait' (CIN-9)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(442): Inlining routine 'nnet::pooling1d_cl<input_t, layer2_t, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(431): Inlining routine 'nnet::pooling1d_buffer_cl<input_t, layer2_t, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(378): Inlining routine 'nnet::compute_pool_buffer_1d<input_t, layer2_t, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_conv_stream.h(161): Inlining routine 'nnet::kernel_shift_1d<input_t, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_types.h(19): Inlining member function 'nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::operator[]' on object 'x' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_types.h(17): Inlining member function 'nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::operator[]' on object 'res_pack' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(17): Inlining routine 'nnet::reduce_pool<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type, 4, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(26): Inlining routine 'nnet::reduce<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type, 4, nnet::Op_add<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type>>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(26): Inlining routine 'nnet::reduce<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type, 2, nnet::Op_add<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type>>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(41): Inlining member function 'nnet::Op_add<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type>::operator()' on object 'op' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(26): Inlining routine 'nnet::reduce<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type, 2, nnet::Op_add<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type>>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(41): Inlining member function 'nnet::Op_add<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type>::operator()' on object 'op' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(41): Inlining member function 'nnet::Op_add<nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::value_type>::operator()' on object 'op' (CIN-64)
# $MGC_HOME/shared/include/ac_fixed.h(1383): Inlining routine 'operator/<32, 12, true, AC_TRN, AC_WRAP>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(348): Inlining routine 'nnet::pooling1d_encoded_cl<input_t, layer2_t, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(269): Inlining routine 'nnet::compute_pool_encoded_1d<input_t, layer2_t, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(29): Inlining routine 'nnet::init_pool_table<4U, 4U>' (CIN-14)
# $MGC_HOME/shared/include/ac_int.h(3403): Inlining routine 'operator><4, false>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_types.h(19): Inlining member function 'nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::operator[]' on object 'x' (CIN-64)
# $MGC_HOME/shared/include/ac_int.h(3404): Inlining routine 'operator==<4, false>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_types.h(17): Inlining member function 'nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::operator[]' on object 'res_pack' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(17): Inlining routine 'nnet::reduce_pool<config2::accum_t, 4, config2>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(26): Inlining routine 'nnet::reduce<config2::accum_t, 4, nnet::Op_add<config2::accum_t>>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(26): Inlining routine 'nnet::reduce<config2::accum_t, 2, nnet::Op_add<config2::accum_t>>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(41): Inlining member function 'nnet::Op_add<config2::accum_t>::operator()' on object 'op' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(26): Inlining routine 'nnet::reduce<config2::accum_t, 2, nnet::Op_add<config2::accum_t>>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(41): Inlining member function 'nnet::Op_add<config2::accum_t>::operator()' on object 'op' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_common.h(41): Inlining member function 'nnet::Op_add<config2::accum_t>::operator()' on object 'op' (CIN-64)
# $MGC_HOME/shared/include/ac_fixed.h(1383): Inlining routine 'operator/<40, 16, true, AC_TRN, AC_WRAP>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_activation_stream.h(56): Inlining routine 'nnet::relu<layer2_t, result_t, relu_config4>' (CIN-14)
# $PROJECT_HOME/firmware/nnet_utils/nnet_types.h(17): Inlining member function 'nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::operator[]' on object 'in_data' (CIN-64)
# $PROJECT_HOME/firmware/nnet_utils/nnet_types.h(17): Inlining member function 'nnet::array<ac_fixed<32, 12, true, AC_TRN, AC_WRAP>, 2U>::operator[]' on object 'out_data' (CIN-64)
# $MGC_HOME/shared/include/ac_math/ac_relu.h(111): Inlining routine 'ac_math::ac_relu<32, 12, true, AC_TRN, AC_WRAP, 32, 12, true, AC_TRN, AC_WRAP>' (CIN-14)
# $MGC_HOME/shared/include/ac_fixed.h(1383): Inlining routine 'operator><32, 12, true, AC_TRN, AC_WRAP>' (CIN-14)
# $PROJECT_HOME/firmware/myproject.cpp(12): Optimizing block '/myproject' ... (CIN-4)
# $PROJECT_HOME/firmware/myproject.cpp(13): INOUT port 'x' is only used as an input. (OPT-10)
# $PROJECT_HOME/firmware/myproject.cpp(14): INOUT port 'layer4_out' is only used as an output. (OPT-11)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(0)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(1)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(2)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(3)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(4)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(5)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(6)' is never driven. (OPT-3)
# Warning: $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(356): Channel 'nnet::pooling1d_encoded_cl<input_t,layer2_t,config2>:data_window(7)' is never driven. (OPT-3)
# $PROJECT_HOME/firmware/nnet_utils/nnet_conv_stream.h(172): Loop '/myproject/core/KernelShiftChannel' iterated at most 2 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_conv_stream.h(169): Loop '/myproject/core/KernelShiftWidth' iterated at most 3 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_conv_stream.h(182): Loop '/myproject/core/KernelPushChannel' iterated at most 2 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(406): Loop '/myproject/core/PoolLoop' iterated at most 4 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(401): Loop '/myproject/core/FiltLoop' iterated at most 2 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_pooling_stream.h(435): Loop '/myproject/core/ReadInputWidth' iterated at most 4 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_activation_stream.h(66): Loop '/myproject/core/ReLUPackLoop' iterated at most 2 times. (LOOP-2)
# $PROJECT_HOME/firmware/nnet_utils/nnet_activation_stream.h(58): Loop '/myproject/core/ReLUActLoop' iterated at most 1 times. (LOOP-2)
# Warning: $PROJECT_HOME/firmware/myproject.cpp(36): Channel '/myproject/layer2_out' (in '/myproject/core') does not cross a hierarchical boundary and can create deadlocks. Downgrade message to warning if desired (HIER-10)
# Design 'myproject' was read (SOL-1)
# Makefile for Original Design + Testbench written to file './scverify/Verify_orig_cxx_osci.mk'
# Info: CDesignChecker Shell script written to '/home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/myproject_prj/myproject.v1/CDesignChecker/design_checker.sh'
# Info: Completed transformation 'compile' on solution 'myproject.v1': elapsed time 6.71 seconds, memory usage 1367304kB, peak memory usage 1367304kB (SOL-9)
# Info: Design complexity at end of 'compile': Total ops = 82, Real ops = 19, Vars = 26 (SOL-21)
# ***** C SIMULATION *****
# Making './scverify/Verify_orig_cxx_osci.mk {} SIMTOOL=osci sim'
# Make utility invoked from '/home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/myproject_prj/myproject.v1'
#     /afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/bin/make -f ./scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci build < "/dev/null" (BASIC-15)
# ============================================
# Creating simulation directory 'scverify/orig_cxx_osci'
# mkdir -p scverify/orig_cxx_osci
# ============================================
# Compiling C++ file: ../../firmware/myproject.cpp
# /afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/dcs_gcc/usr/bin/g++ -DCCS_SCVERIFY_USE_CCS_BLOCK -DCCS_DUT_SYSC -DRANDOM_FRAMES=5 -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION -std=gnu++17 -Wall -Wno-unknown-pragmas -Wno-unused-label -g -I. -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include/nnet_utils -I../.. -I. -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include/nnet_utils -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/hls_pkgs/src -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/siflibs -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DSC_USE_STD_STRING  -c ..
# /../firmware/myproject.cpp -o scverify/orig_cxx_osci/myproject.cpp.cxxts.o
# In file included from ../../firmware/parameters.h:13,
#                  from ../../firmware/myproject.cpp:4:
# ../../firmware/nnet_utils/nnet_pooling_stream.h: In instantiation of ‘void nnet::compute_pool_encoded_1d(unsigned int, const data_T&, ac_channel<typename data_T::value_type>*, ac_channel<dstType>&, res_T&, unsigned int&) [with data_T = nnet::array<ac_fixed<32, 12, true>, 2>; res_T = nnet::array<ac_fixed<32, 12, true>, 2>; CONFIG_T = config2; typename data_T::value_type = ac_fixed<32, 12, true>]’:
# ../../firmware/nnet_utils/nnet_pooling_stream.h:370:57:   required from ‘void nnet::pooling1d_encoded_cl(ac_channel<T>&, ac_channel<dstType>&) [with data_T = nnet::array<ac_fixed<32, 12, true>, 2>; res_T = nnet::array<ac_fixed<32, 12, true>, 2>; CONFIG_T = config2]’
# ../../firmware/nnet_utils/nnet_pooling_stream.h:449:54:   required from ‘void nnet::pooling1d_cl(ac_channel<T>&, ac_channel<dstType>&) [with data_T = nnet::array<ac_fixed<32, 12, true>, 2>; res_T = nnet::array<ac_fixed<32, 12, true>, 2>; CONFIG_T = config2]’
# ../../firmware/myproject.cpp:38:65:   required from here
# ../../firmware/nnet_utils/nnet_pooling_stream.h:276:24: warning: unused variable ‘sW’ [-Wunused-variable]
#   276 |     constexpr unsigned sW =
#       |                        ^~
# ============================================
# Compiling C++ file: ../../myproject_test.cpp
# /afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/dcs_gcc/usr/bin/g++ -DCCS_SCVERIFY_USE_CCS_BLOCK -DCCS_DUT_SYSC -DRANDOM_FRAMES=5 -DSC_INCLUDE_DYNAMIC_PROCESSES -DSC_USE_STD_STRING -DCCS_MISMATCHED_OUTPUTS_ONLY -DDEADLOCK_DETECTION -std=gnu++17 -Wall -Wno-unknown-pragmas -Wno-unused-label -g -I. -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include/nnet_utils -I../.. -I. -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include/nnet_utils -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/include -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/hls_pkgs/src -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/siflibs -I/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/hls_pkgs/mgc_comps_src -DSC_USE_STD_STRING  -c ..
# /../myproject_test.cpp -o scverify/orig_cxx_osci/myproject_test.cpp.cxxts.o
# ============================================
# Linking executable
# /afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/pkgs/dcs_gcc/usr/bin/g++  -B/usr/lib/x86_64-linux-gnu -static-libstdc++ -L/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/lib/Linux/gcc-10.3.0-64 -L/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/lib -L/afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/shared/lib/Linux/gcc-10.3.0-64 scverify/orig_cxx_osci/myproject.cpp.cxxts.o scverify/orig_cxx_osci/myproject_test.cpp.cxxts.o -Wl,-Bstatic -lsystemc -Wl,-Bdynamic -lpthread -o scverify/orig_cxx_osci/scverify_top
#     /afs/ece.cmu.edu/support/mgc/mgc.release/catapult_synth_2024.2/Mgc_home/bin/make -f ./scverify/Verify_orig_cxx_osci.mk SIMTOOL=osci sim (BASIC-14)
# ============================================
# Simulating design
# cd ../..; ./myproject_prj/myproject.v1/scverify/orig_cxx_osci/scverify_top ./firmware/weights ./tb_data/./tb_input_features.dat ./tb_data/./tb_output_predictions.dat
#   Weights directory: ./firmware/weights
#   Test Feature Data: ./tb_data/./tb_input_features.dat
#   Test Predictions : ./tb_data/./tb_output_predictions.dat
# Processing input 0
# Predictions
# 0.588671 0.103337 
# Quantized predictions
# .5886707305908203125 .103336334228515625 
# Processing input 1
# Predictions
# 0.487927 0.592197 
# Quantized predictions
# .487926483154296875 .5921955108642578125 
# Processing input 2
# Predictions
# 0.735344 0.439461 
# Quantized predictions
# .73534297943115234375 .43945980072021484375 
# Info: Saved inference results to file: tb_data/csim_results.log
# ***** C SIMULATION COMPLETED IN 0h0m7s *****
# ***** SETTING TECHNOLOGY LIBRARIES *****
# Library Name: mgc_Xilinx-KINTEX-u-2_beh
# Library Path: /CONFIG/PARAMETERS/Vivado/PARAMETERS/Xilinx/PARAMETERS/KINTEX-u/PARAMETERS/-2/PARAMETERS/xcku115-flvb2104-2-i/LIBRARIES/99/NAME
# ***** C/RTL SYNTHESIS *****
# Info: Starting transformation 'libraries' on solution 'myproject.v1' (SOL-8)
# Info: Please set ComponentLibs/TechLibSearchPath to enable flows that use downstream synthesis tools (LIB-220)
# Reading component library '$MGC_HOME/pkgs/siflibs/mgc_busdefs.lib' [mgc_busdefs]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/siflibs/stdops.lib' [STDOPS]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/siflibs/fpops.lib' [FPOPS]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/siflibs/ccs_dw_ops.lib' [CCS_DW_OPS]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/siflibs/ccs_ioport.lib' [ccs_ioport]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/siflibs/mgc_ioport.lib' [mgc_ioport]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/cds_assert/assert_ops.lib' [ASSERT_OPS]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/cds_assert/assert_mods.lib' [assert_mods]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/siflibs/ccs_connections.lib' [ccs_connections]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/ccs_xilinx/mgc_Xilinx-KINTEX-u-2_beh.lib' [mgc_Xilinx-KINTEX-u-2_beh]... (LIB-49)
# Warning: Detected an old component library 'mgc_Xilinx-KINTEX-u-2_beh' - it is recommended that the user update this component library to the latest version. It can be done by reading this old component library in Catapult Library Builder (2024.2_2/1156857 or later) and saving the library into the target file. (LIB-82)
# Reading component library '$MGC_HOME/pkgs/ccs_xilinx/Xilinx_RAMS.lib' [Xilinx_RAMS]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/ccs_xilinx/Xilinx_ROMS.lib' [Xilinx_ROMS]... (LIB-49)
# Reading component library '$MGC_HOME/pkgs/ccs_xilinx/Xilinx_FIFO.lib' [Xilinx_FIFO]... (LIB-49)
# Info: Completed transformation 'libraries' on solution 'myproject.v1': elapsed time 0.81 seconds, memory usage 1367304kB, peak memory usage 1367304kB (SOL-9)
# Info: Design complexity at end of 'libraries': Total ops = 82, Real ops = 19, Vars = 26 (SOL-21)
# Info: Starting transformation 'assembly' on solution 'myproject.v1' (SOL-8)
# Error: $PROJECT_HOME/firmware/myproject.cpp(36): Using Channel 'layer2_out' as both input and output is unsupported. (HIER-11)
# Info: Completed transformation 'libraries' on solution 'myproject.v1': elapsed time 0.19 seconds, memory usage 1367304kB, peak memory usage 1367304kB (SOL-9)
# Info: Design complexity at end of 'libraries': Total ops = 88, Real ops = 20, Vars = 33 (SOL-21)
# > end dofile ./build_prj.tcl
# Error: go: Transformation 'assembly' failed
Utilization report not found.
Timing report not found.
Results in nnet_layer_results.txt from: /home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/myproject_prj/myproject.v1/nnet_layer_results.txt
Traceback (most recent call last):
  File "/home/asicflow-user/work/ece-18-725/ResNet/python/test_pool_squeeze.py", line 120, in <module>
    hls_model.build(csim=True, synth=True, cosim=True, validation=True)
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/model/graph.py", line 1001, in build
    return self.config.backend.build(self, **kwargs)
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/backends/catapult/catapult_backend.py", line 259, in build
    return parse_catapult_report(model.config.get_output_dir())
  File "/home/asicflow-user/miniconda3/envs/hls4ml/lib/python3.10/site-packages/hls4ml/report/catapult_report.py", line 224, in parse_catapult_report
    with open(file_path) as file:
FileNotFoundError: [Errno 2] No such file or directory: '/home/asicflow-user/work/ece-18-725/ResNet/python/hls4mlprj_pool_squeeze_Catapult_io_stream/myproject_prj/myproject.v1/nnet_layer_results.txt'

[sei-jgwohlbier]

Full circle to #1180