fixing discrepancies post-merge

Author: alex-yang-upenn

hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py

@@ -8,37 +8,6 @@ def __init__(self):
         self._register_layer_attributes()
         self._register_flows()
 
-    def create_initial_config(
-        self,
-        board='alveo-u55c',
-        part=None,
-        clock_period=5,
-        io_type='io_parallel',
-        num_kernel=1,
-        num_thread=1,
-        batchsize=8192
-    ):
-        '''
-        Create initial accelerator config with default parameters
-
-        Args:
-            board: one of the keys defined in supported_boards.json
-            clock_period: clock period passed to hls project
-            io_type: io_parallel or io_stream
-            num_kernel: how many compute units to create on the fpga
-            num_thread: how many threads the host cpu uses to drive the fpga
-        Returns:
-            populated config
-        '''
-        board = board if board is not None else 'alveo-u55c'
-        config = super().create_initial_config(part, clock_period, io_type)
-        config['AcceleratorConfig'] = {}
-        config['AcceleratorConfig']['Board'] = board
-        config['AcceleratorConfig']['Num_Kernel'] = num_kernel
-        config['AcceleratorConfig']['Num_Thread'] = num_thread
-        config['AcceleratorConfig']['Batchsize'] = batchsize
-        return config
-
     def _register_flows(self):
         validation_passes = [
             'vitisaccelerator:validate_conv_implementation',
@@ -59,18 +28,16 @@ def _register_flows(self):
         ip_flow_requirements.insert(ip_flow_requirements.index('vivado:apply_templates'), template_flow)
 
         self._default_flow = register_flow('ip', None, requires=ip_flow_requirements, backend=self.name)
-
+    
     def create_initial_config(
         self,
-        board='pynq-z2',
+        board='alveo-u55c',
         part=None,
         clock_period=5,
         io_type='io_parallel',
-        interface='axi_stream',
-        driver='python',
-        input_type='float',
-        output_type='float',
-        platform='xilinx_u250_xdma_201830_2',
+        num_kernel=1,
+        num_thread=1,
+        batchsize=8192
     ):
         '''
         Create initial accelerator config with default parameters
@@ -79,32 +46,16 @@ def create_initial_config(
             board: one of the keys defined in supported_boards.json
             clock_period: clock period passed to hls project
             io_type: io_parallel or io_stream
-            interface: `axi_stream`: generate hardware designs and drivers which exploit axi stream channels.
-                       `axi_master`: generate hardware designs and drivers which exploit axi master channels.
-                       `axi_lite` : generate hardware designs and drivers which exploit axi lite channels. (Don't use it
-                       to exchange large amount of data)
-            driver: `python`: generates the python driver to use the accelerator in the PYNQ stack.
-                    `c`: generates the c driver to use the accelerator bare-metal.
-            input_type: the wrapper input precision. Can be `float` or an `ap_type`. Note: VivadoAcceleratorBackend
-                             will round the number of bits used to the next power-of-2 value.
-            output_type: the wrapper output precision. Can be `float` or an `ap_type`. Note:
-                              VivadoAcceleratorBackend will round the number of bits used to the next power-of-2 value.
-            platform: development target platform
-
+            num_kernel: how many compute units to create on the fpga
+            num_thread: how many threads the host cpu uses to drive the fpga
         Returns:
             populated config
         '''
-        board = board if board is not None else 'pynq-z2'
+        board = board if board is not None else 'alveo-u55c'
         config = super().create_initial_config(part, clock_period, io_type)
         config['AcceleratorConfig'] = {}
         config['AcceleratorConfig']['Board'] = board
-        config['AcceleratorConfig']['Interface'] = interface  # axi_stream, axi_master, axi_lite
-        config['AcceleratorConfig']['Driver'] = driver
-        config['AcceleratorConfig']['Precision'] = {}
-        config['AcceleratorConfig']['Precision']['Input'] = {}
-        config['AcceleratorConfig']['Precision']['Output'] = {}
-        config['AcceleratorConfig']['Precision']['Input'] = input_type  # float, double or ap_fixed<a,b>
-        config['AcceleratorConfig']['Precision']['Output'] = output_type  # float, double or ap_fixed<a,b>
-        config['AcceleratorConfig']['Platform'] = platform
-
-        return config
+        config['AcceleratorConfig']['Num_Kernel'] = num_kernel
+        config['AcceleratorConfig']['Num_Thread'] = num_thread
+        config['AcceleratorConfig']['Batchsize'] = batchsize
+        return config

hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py

@@ -1,3 +1,6 @@
+import json
+import os
+
 class VitisAcceleratorConfig:
     def __init__(self, config):
         self.config = config.config