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alex-yang-upennQuentin Berthet
alex-yang-upenn
authored and
Quentin Berthet
committed
Default directives + HLS Clock control
1 parent 728f914 commit bf88255

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5 files changed

+172
-23
lines changed

5 files changed

+172
-23
lines changed

‎hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,8 @@ def create_initial_config(
2121
io_type='io_parallel',
2222
num_kernel=1,
2323
num_thread=1,
24-
batchsize=8192
24+
batchsize=8192,
25+
vivado_directives=[]
2526
):
2627
'''
2728
Create initial accelerator config with default parameters
@@ -32,6 +33,8 @@ def create_initial_config(
3233
io_type: io_parallel or io_stream
3334
num_kernel: how many compute units to create on the fpga
3435
num_thread: how many threads the host cpu uses to drive the fpga
36+
batchsize: how many samples to process within a single buffer on the fpga
37+
vivado_directives: Directives passed down to Vivado that controls the hardware synthesis and implementation steps
3538
Returns:
3639
populated config
3740
'''
@@ -42,9 +45,10 @@ def create_initial_config(
4245
config['AcceleratorConfig']['Num_Kernel'] = num_kernel
4346
config['AcceleratorConfig']['Num_Thread'] = num_thread
4447
config['AcceleratorConfig']['Batchsize'] = batchsize
48+
config['AcceleratorConfig']['Vivado_Directives'] = vivado_directives
4549
return config
4650

47-
def build(self, model, reset=False, synth=True, vsynth=True):
51+
def build(self, model, reset=False, synth=True, vsynth=True, **kwargs):
4852
if 'linux' in sys.platform:
4953
if 'XILINX_VITIS' not in os.environ:
5054
raise Exception("XILINX_VITIS environmental variable missing. Please install XRT and Vitis, and run the setup scripts before building")

‎hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,9 @@ def __init__(self, config):
3131

3232
self.num_kernel = accel_config.get('Num_Kernel')
3333
self.num_thread = accel_config.get('Num_Thread')
34-
self.batchsize = accel_config.get('Batchsize')
34+
self.batchsize = accel_config.get('Batchsize')
35+
36+
self.vivado_directives = accel_config.get('Vivado_Directives')
3537

3638
def get_board_type(self):
3739
return self.board_type
@@ -53,3 +55,6 @@ def get_memory_type(self):
5355

5456
def get_memory_channel_count(self):
5557
return self.memory_channel_count
58+
59+
def get_vivado_directives(self):
60+
return self.vivado_directives

‎hls4ml/backends/vitis_accelerator/vivado_directives.json

Lines changed: 137 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,137 @@
1+
{
2+
"impl.strategies": [
3+
"Performance_Explore",
4+
"Performance_ExplorePostRoutePhysOpt",
5+
"Performance_LBlockPlacement",
6+
"Performance_LBlockPlacementFanoutOpt",
7+
"Performance_NetDelay_high",
8+
"Performance_NetDelay_low",
9+
"Performance_Retiming",
10+
"Performance_ExtraTimingOpt",
11+
"Performance_RefinePlacement",
12+
"Performance_SpreadSLL",
13+
"Performance_BalanceSLL",
14+
"Congestion_SpreadLogic_high",
15+
"Congestion_SpreadLogic_medium",
16+
"Congestion_SpreadLogic_low",
17+
"Congestion_SpreadLogic_Explore",
18+
"Congestion_SSI_SpreadLogic_high",
19+
"Congestion_SSI_SpreadLogic_low",
20+
"Area_Explore",
21+
"Area_ExploreSequential",
22+
"Area_ExploreWithRemap",
23+
"Power_DefaultOpt",
24+
"Power_ExploreArea",
25+
"Flow_RunPhysOpt",
26+
"Flow_RunPostRoutePhysOpt",
27+
"Flow_RuntimeOptimized",
28+
"Flow_Quick",
29+
"ALL"
30+
],
31+
"prop": {
32+
"run": {
33+
"impl": {
34+
"STEPS": {
35+
"OPT_DESIGN": {
36+
"ARGS": {
37+
"DIRECTIVE": [
38+
"Explore",
39+
"ExploreArea",
40+
"ExploreSequentialArea",
41+
"RuntimeOptimized",
42+
"ExploreWithRemap"
43+
]
44+
}
45+
},
46+
"POWER_OPT_DESIGN": {
47+
"IS_ENABLED": [
48+
"true"
49+
]
50+
},
51+
"PLACE_DESIGN": {
52+
"ARGS": {
53+
"DIRECTIVE": [
54+
"Explore",
55+
"WLDrivenBlockPlacement",
56+
"EarlyBlockPlacement",
57+
"ExtraNetDelay_high",
58+
"ExtraNetDelay_low",
59+
"SSI_SpreadLogic_high",
60+
"SSI_SpreadLogic_low",
61+
"AltSpreadLogic_high",
62+
"AltSpreadLogic_medium",
63+
"AltSpreadLogic_low",
64+
"ExtraPostPlacementOpt",
65+
"ExtraTimingOpt",
66+
"SSI_SpreadSLLs",
67+
"SSI_BalanceSLLs",
68+
"SSI_Balance_SLRs",
69+
"SSI_HighUtilSLRs",
70+
"RuntimeOptimized",
71+
"Quick",
72+
"Auto_1",
73+
"Auto_2",
74+
"Auto_3"
75+
]
76+
}
77+
},
78+
"POST_PLACE_POWER_OPT_DESIGN": {
79+
"IS_ENABLED": [
80+
"true"
81+
]
82+
},
83+
"PHYS_OPT_DESIGN": {
84+
"IS_ENABLED": [
85+
"true"
86+
],
87+
"ARGS": {
88+
"DIRECTIVE": [
89+
"Explore",
90+
"ExploreWithHoldFix",
91+
"ExploreWithAggressiveHoldFix",
92+
"AggressiveExplore",
93+
"AlternateReplication",
94+
"AggressiveFanoutOpt",
95+
"AddRetime",
96+
"AlternateFlowWithRetiming",
97+
"RuntimeOptimized"
98+
]
99+
}
100+
},
101+
"ROUTE_DESIGN": {
102+
"ARGS": {
103+
"DIRECTIVE": [
104+
"Explore",
105+
"AggressiveExplore",
106+
"NoTimingRelaxation",
107+
"MoreGlobalIterations",
108+
"HigherDelayCost",
109+
"RuntimeOptimized",
110+
"AlternateCLBRouting",
111+
"Quick"
112+
]
113+
}
114+
},
115+
"POST_ROUTE_PHYS_OPT_DESIGN": {
116+
"IS_ENABLED": [
117+
"true"
118+
],
119+
"ARGS": {
120+
"DIRECTIVE": [
121+
"Explore",
122+
"ExploreWithHoldFix",
123+
"ExploreWithAggressiveHoldFix",
124+
"AggressiveExplore",
125+
"AlternateReplication",
126+
"AggressiveFanoutOpt",
127+
"AddRetime",
128+
"AlternateFlowWithRetiming",
129+
"RuntimeOptimized"
130+
]
131+
}
132+
}
133+
}
134+
}
135+
}
136+
}
137+
}

‎hls4ml/templates/vitis_accelerator/accelerator_card.cfg

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8,19 +8,8 @@ prop=kernel.kernel_wrapper.kernel_flags=-std=c++11
88

99
[hls]
1010
pre_tcl=./hls_config.tcl
11+
# hls-fpga-machine-learning clock control
1112

1213
# hls-fpga-machine-learning kernel control
1314

14-
[vivado]
15-
prop=run.impl_1.STEPS.OPT_DESIGN.IS_ENABLED=true
16-
prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore
17-
18-
prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high
19-
20-
prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true
21-
prop=run.imp1_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
22-
23-
prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore
24-
25-
prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true
26-
prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
15+
# hls-fpga-machine-learning vivado directives

‎hls4ml/writer/vitis_accelerator_writer.py

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -230,13 +230,18 @@ def write_accelerator_card_cfg(self, model):
230230
raise Exception(format(self.vitis_accelerator_config.get_platform()) +
231231
' has only ' + format(num_channels) + ' memory banks.')
232232

233+
directives = self.vitis_accelerator_config.get_vivado_directives()
234+
233235
for line in f.readlines():
234236
if 'MYPLATFORM' in line:
235237
newline = line.replace('MYPLATFORM', format(self.vitis_accelerator_config.get_platform()))
238+
elif "# hls-fpga-machine-learning clock control" in line:
239+
freq = round(1e9 / model.config.get_config_value('ClockPeriod'))
240+
newline = 'clock={}:kernel_wrapper\n'.format(freq)
236241
elif '# hls-fpga-machine-learning kernel control' in line:
237242
newline = '[connectivity]\n'
238243
newline += 'nk=kernel_wrapper:' + format(num_kernels) + '\n\n'
239-
if self.vitis_accelerator_config.get_board_type() == "alveo":
244+
if self.vitis_accelerator_config.get_board_type() == 'alveo':
240245
if memory_type == 'hbm':
241246
for i in range(0, num_kernels):
242247
newline += 'sp=kernel_wrapper_{}.in:HBM[{}:{}]\n'.format(i + 1, (i*2)*num_channels_per_cu, ((i*2 + 1)*num_channels_per_cu) - 1)
@@ -248,18 +253,27 @@ def write_accelerator_card_cfg(self, model):
248253
newline += '\n'
249254
for i in range(0, num_kernels):
250255
newline += 'slr=kernel_wrapper_{}:SLR{}\n'.format(i + 1, i)
256+
elif '# hls-fpga-machine-learning vivado directives' in line:
257+
newline = ''
258+
if directives:
259+
newline += '[vivado]\n'
260+
for x in directives:
261+
newline += x + '\n'
251262
else:
252263
newline = line
253264
fout.write(newline)
254265
f.close()
255266
fout.close()
256267

257-
# Copy hls_config.tcl
258-
filedir = os.path.dirname(os.path.abspath(__file__))
259-
srcpath = os.path.join(filedir, '../templates/vitis_accelerator/hls_config.tcl')
260-
dstpath = f'{model.config.get_output_dir()}/hls_config.tcl'
261-
copy(srcpath, dstpath)
262-
268+
# Write hls_config.tcl
269+
tcl_f = open(os.path.join(filedir, '../templates/vitis_accelerator/hls_config.tcl'))
270+
tcl_fout = open(f'{model.config.get_output_dir()}/hls_config.tcl', 'w')
271+
for line in tcl_f.readlines():
272+
newline = line
273+
tcl_fout.write(newline)
274+
tcl_fout.write('\nset_clock_uncertainty {}\n'.format(model.config.get_config_value('ClockUncertainty', '12.5%')))
275+
tcl_f.close()
276+
tcl_fout.close()
263277

264278
def write_nnet_utils_overrides(self, model):
265279
"""Override nnet_types.h pointer comparison

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