Merge pull request #986 from vloncar/namespaces_and_other_emulator_goodies

Add namespaces and optional writer config

Author: jmitrevs

hls4ml/backends/vitis/vitis_backend.py

@@ -34,15 +34,44 @@ def _register_flows(self):
         self._default_flow = register_flow('ip', None, requires=ip_flow_requirements, backend=self.name)
 
     def create_initial_config(
-        self, part='xcvu13p-flga2577-2-e', clock_period=5, clock_uncertainty='27%', io_type='io_parallel', **_
+        self,
+        part='xcvu13p-flga2577-2-e',
+        clock_period=5,
+        clock_uncertainty='27%',
+        io_type='io_parallel',
+        namespace=None,
+        write_weights_txt=True,
+        write_tar=False,
+        **_,
     ):
+        """Create initial configuration of the Vitis backend.
+
+        Args:
+            part (str, optional): The FPGA part to be used. Defaults to 'xcvu13p-flga2577-2-e'.
+            clock_period (int, optional): The clock period. Defaults to 5.
+            clock_uncertainty (str, optional): The clock uncertainty. Defaults to 27%.
+            io_type (str, optional): Type of implementation used. One of
+                'io_parallel' or 'io_stream'. Defaults to 'io_parallel'.
+            namespace (str, optional): If defined, place all generated code within a namespace. Defaults to None.
+            write_weights_txt (bool, optional): If True, writes weights to .txt files which speeds up compilation.
+                Defaults to True.
+            write_tar (bool, optional): If True, compresses the output directory into a .tar.gz file. Defaults to False.
+
+        Returns:
+            dict: initial configuration.
+        """
         config = {}
 
         config['Part'] = part if part is not None else 'xcvu13p-flga2577-2-e'
         config['ClockPeriod'] = clock_period if clock_period is not None else 5
         config['ClockUncertainty'] = clock_uncertainty if clock_uncertainty is not None else '27%'
         config['IOType'] = io_type if io_type is not None else 'io_parallel'
         config['HLSConfig'] = {}
+        config['WriterConfig'] = {
+            'Namespace': namespace,
+            'WriteWeightsTxt': write_weights_txt,
+            'WriteTar': write_tar,
+        }
 
         return config
 

hls4ml/backends/vivado/vivado_backend.py

@@ -175,15 +175,44 @@ def get_writer_flow(self):
         return self._writer_flow
 
     def create_initial_config(
-        self, part='xcvu13p-flga2577-2-e', clock_period=5, clock_uncertainty='12.5%', io_type='io_parallel', **_
+        self,
+        part='xcvu13p-flga2577-2-e',
+        clock_period=5,
+        clock_uncertainty='12.5%',
+        io_type='io_parallel',
+        namespace=None,
+        write_weights_txt=True,
+        write_tar=False,
+        **_,
     ):
+        """Create initial configuration of the Vivado backend.
+
+        Args:
+            part (str, optional): The FPGA part to be used. Defaults to 'xcvu13p-flga2577-2-e'.
+            clock_period (int, optional): The clock period. Defaults to 5.
+            clock_uncertainty (str, optional): The clock uncertainty. Defaults to 12.5%.
+            io_type (str, optional): Type of implementation used. One of
+                'io_parallel' or 'io_stream'. Defaults to 'io_parallel'.
+            namespace (str, optional): If defined, place all generated code within a namespace. Defaults to None.
+            write_weights_txt (bool, optional): If True, writes weights to .txt files which speeds up compilation.
+                Defaults to True.
+            write_tar (bool, optional): If True, compresses the output directory into a .tar.gz file. Defaults to False.
+
+        Returns:
+            dict: initial configuration.
+        """
         config = {}
 
         config['Part'] = part if part is not None else 'xcvu13p-flga2577-2-e'
         config['ClockPeriod'] = clock_period if clock_period is not None else 5
         config['ClockUncertainty'] = clock_uncertainty if clock_uncertainty is not None else '12.5%'
         config['IOType'] = io_type if io_type is not None else 'io_parallel'
         config['HLSConfig'] = {}
+        config['WriterConfig'] = {
+            'Namespace': namespace,
+            'WriteWeightsTxt': write_weights_txt,
+            'WriteTar': write_tar,
+        }
 
         return config
 

hls4ml/model/graph.py

@@ -51,6 +51,15 @@ def __init__(self, config):
 
         self.pipeline_style = 'pipeline'
 
+        if 'WriterConfig' in self.config:
+            self.writer_config = self.config['WriterConfig']
+        else:
+            self.writer_config = {
+                'Namespace': None,
+                'WriteWeightsTxt': True,
+                'WriteTar': False,
+            }
+
         self._parse_hls_config()
         self._validate_hls_config()
 
@@ -183,6 +192,9 @@ def get_compression(self, layer):
 
         return compression
 
+    def get_writer_config(self):
+        return self.writer_config
+
     def _parse_hls_config(self):
         hls_config = self.config['HLSConfig']
 

hls4ml/templates/vivado/firmware/defines.h

@@ -9,6 +9,10 @@
 
 // hls-fpga-machine-learning insert numbers
 
+// hls-fpga-machine-learning insert namespace-start
+
 // hls-fpga-machine-learning insert layer-precision
 
+// hls-fpga-machine-learning insert namespace-end
+
 #endif

hls4ml/templates/vivado/firmware/myproject.cpp

@@ -3,23 +3,21 @@
 #include "myproject.h"
 #include "parameters.h"
 
+// hls-fpga-machine-learning insert namespace-start
+
 void myproject(
     // hls-fpga-machine-learning insert header
 ) {
 
     // hls-fpga-machine-learning insert IO
 
-#ifndef __SYNTHESIS__
-    static bool loaded_weights = false;
-    if (!loaded_weights) {
-        // hls-fpga-machine-learning insert load weights
-        loaded_weights = true;
-    }
-#endif
+    // hls-fpga-machine-learning insert load weights
 
     // ****************************************
     // NETWORK INSTANTIATION
     // ****************************************
 
     // hls-fpga-machine-learning insert layers
 }
+
+// hls-fpga-machine-learning insert namespace-end

hls4ml/templates/vivado/firmware/myproject.h

@@ -7,9 +7,13 @@
 
 #include "defines.h"
 
+// hls-fpga-machine-learning insert namespace-start
+
 // Prototype of top level function for C-synthesis
 void myproject(
     // hls-fpga-machine-learning insert header
 );
 
+// hls-fpga-machine-learning insert namespace-end
+
 #endif

hls4ml/templates/vivado/firmware/parameters.h

@@ -10,6 +10,10 @@
 
 // hls-fpga-machine-learning insert weights
 
+// hls-fpga-machine-learning insert namespace-start
+
 // hls-fpga-machine-learning insert layer-config
 
+// hls-fpga-machine-learning insert namespace-end
+
 #endif

hls4ml/templates/vivado/myproject_bridge.cpp

@@ -52,13 +52,16 @@ void collect_trace_output(struct trace_data *c_trace_outputs) {
 void myproject_float(
     // hls-fpga-machine-learning insert header #float
 ) {
+    // hls-fpga-machine-learning insert namespace
 
     // hls-fpga-machine-learning insert wrapper #float
 }
 
 void myproject_double(
     // hls-fpga-machine-learning insert header #double
 ) {
+    // hls-fpga-machine-learning insert namespace
+
     // hls-fpga-machine-learning insert wrapper #double
 }
 }

hls4ml/templates/vivado/myproject_test.cpp

@@ -21,6 +21,8 @@ size_t trace_type_size = sizeof(double);
 } // namespace nnet
 
 int main(int argc, char **argv) {
+    // hls-fpga-machine-learning insert namespace
+
     // load input data from text file
     std::ifstream fin("tb_data/tb_input_features.dat");
     // load predictions from text file

hls4ml/writer/vitis_writer.py

@@ -30,5 +30,4 @@ def write_hls(self, model):
         """
         super().write_hls(model)
         self.write_nnet_utils_overrides(model)
-        os.remove(model.config.get_output_dir() + '.tar.gz')
         self.write_tar(model)