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Merge branch 'vitis_accelerator_dev' into makefile_update
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‎docs/advanced/accelerator.rst

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@@ -75,3 +75,50 @@ The ``predict`` method will send the input data to the PL and return the output
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nn = NeuralNetworkOverlay('hls4ml_nn.bit', X_test.shape, y_test.shape)
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y_hw, latency, throughput = nn.predict(X_test, profile=True)
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========================
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VitisAccelerator Backend
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========================
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The ``VitsAccelerator`` backned makes use of the vitis kernel flow to and streamlines the generation of an hls4ml project targeting PCIe accelerators.
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Vitis accelerator backend supports the following boards:
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* `Alveo u50 <https://www.xilinx.com/products/boards-and-kits/alveo/u50.html>`_
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* `Alveo u55c <https://www.xilinx.com/products/boards-and-kits/alveo/u55c.html>`_
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* `Alveo u250 <https://www.xilinx.com/products/boards-and-kits/alveo/u250.html>`_
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* `Versal vck5000 <https://www.xilinx.com/products/boards-and-kits/vck5000.html>`_
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The backend also generates an `OpenCL` host code that uploads and runs the kernel on the accelerator card.
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Example
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=======
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The following example is a modified version of `hsl4ml example 7 <https://github.com/fastmachinelearning/hls4ml-tutorial/blob/master/part7_deployment.ipynb>`_.
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.. code-block:: Python
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import hls4ml
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hls_model = hls4ml.converters.convert_from_keras_model(
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model,
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hls_config=config,
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output_dir='model_3/hls4ml_prj_vitis_accel',
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backend='VitisAccelerator',
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board='alveo-u55c',
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num_kernel=4,
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num_thread=8,
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batchsize=8192
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)
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hls_model.compile()
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hls_model.build()
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By default the build method generates all the necessary files to run the kernel on the accelerator board. As this can be a long process, there are three build options that target the generation of specific parts of the project:
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* `host`: Compiles the host application
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* `hls`: Produces only the kernel's object file
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* `xclbin`: Produces only the kernel's .xclbin file
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The generated host code application and the xclbin file can be executed as such:
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.. code-block:: Bash
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./host <myproject>.xclbin

‎hls4ml/backends/vitis_accelerator/supported_boards.json

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@@ -18,8 +18,8 @@
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"memory": {"type": "ddr", "channels": 4, "capacity": 64}
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},
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"vck5000": {
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"board_type": "alveo-versal",
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"part": "xcvc1902-2msevsvd1760",
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"board_type": "versal",
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"part": "xcvc1902-vsvd1760-2MP-e-S",
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"platform": "xilinx_vck5000_gen4x8_qdma_2_202220_1",
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"memory":{"type": "ddr", "channels": 3, "capacity": 12}
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}

‎hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py

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@@ -21,7 +21,8 @@ def create_initial_config(
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io_type='io_parallel',
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num_kernel=1,
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num_thread=1,
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batchsize=8192
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batchsize=8192,
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vivado_directives=[]
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):
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'''
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Create initial accelerator config with default parameters
@@ -32,6 +33,8 @@ def create_initial_config(
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io_type: io_parallel or io_stream
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num_kernel: how many compute units to create on the fpga
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num_thread: how many threads the host cpu uses to drive the fpga
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batchsize: how many samples to process within a single buffer on the fpga
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vivado_directives: Directives passed down to Vivado that controls the hardware synthesis and implementation steps
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Returns:
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populated config
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'''
@@ -42,6 +45,7 @@ def create_initial_config(
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config['AcceleratorConfig']['Num_Kernel'] = num_kernel
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config['AcceleratorConfig']['Num_Thread'] = num_thread
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config['AcceleratorConfig']['Batchsize'] = batchsize
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config['AcceleratorConfig']['Vivado_Directives'] = vivado_directives
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return config
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def build(self, model, reset=False, synth=True, vsynth=True, csim=False, cosim=False, debug=False, **kwargs):

‎hls4ml/backends/vitis_accelerator/vitis_accelerator_config.py

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@@ -30,7 +30,9 @@ def __init__(self, config):
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self.num_kernel = accel_config.get('Num_Kernel')
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self.num_thread = accel_config.get('Num_Thread')
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self.batchsize = accel_config.get('Batchsize')
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self.batchsize = accel_config.get('Batchsize')
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self.vivado_directives = accel_config.get('Vivado_Directives')
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def get_board_type(self):
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return self.board_type
@@ -52,3 +54,6 @@ def get_memory_type(self):
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def get_memory_channel_count(self):
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return self.memory_channel_count
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def get_vivado_directives(self):
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return self.vivado_directives

‎hls4ml/backends/vitis_accelerator/vivado_directives.json

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{
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"impl.strategies": [
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"Performance_Explore",
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"Performance_ExplorePostRoutePhysOpt",
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"Performance_LBlockPlacement",
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"Performance_LBlockPlacementFanoutOpt",
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"Performance_NetDelay_high",
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"Performance_NetDelay_low",
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"Performance_Retiming",
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"Performance_ExtraTimingOpt",
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"Performance_RefinePlacement",
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"Performance_SpreadSLL",
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"Performance_BalanceSLL",
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"Congestion_SpreadLogic_high",
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"Congestion_SpreadLogic_medium",
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"Congestion_SpreadLogic_low",
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"Congestion_SpreadLogic_Explore",
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"Congestion_SSI_SpreadLogic_high",
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"Congestion_SSI_SpreadLogic_low",
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"Area_Explore",
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"Area_ExploreSequential",
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"Area_ExploreWithRemap",
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"Power_DefaultOpt",
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"Power_ExploreArea",
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"Flow_RunPhysOpt",
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"Flow_RunPostRoutePhysOpt",
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"Flow_RuntimeOptimized",
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"Flow_Quick",
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"ALL"
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],
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"prop": {
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"run": {
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"impl": {
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"STEPS": {
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"OPT_DESIGN": {
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"ARGS": {
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"DIRECTIVE": [
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"Explore",
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"ExploreArea",
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"ExploreSequentialArea",
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"RuntimeOptimized",
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"ExploreWithRemap"
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]
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}
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},
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"POWER_OPT_DESIGN": {
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"IS_ENABLED": [
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"true"
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]
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},
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"PLACE_DESIGN": {
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"ARGS": {
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"DIRECTIVE": [
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"Explore",
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"WLDrivenBlockPlacement",
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"EarlyBlockPlacement",
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"ExtraNetDelay_high",
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"ExtraNetDelay_low",
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"SSI_SpreadLogic_high",
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"SSI_SpreadLogic_low",
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"AltSpreadLogic_high",
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"AltSpreadLogic_medium",
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"AltSpreadLogic_low",
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"ExtraPostPlacementOpt",
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"ExtraTimingOpt",
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"SSI_SpreadSLLs",
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"SSI_BalanceSLLs",
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"SSI_Balance_SLRs",
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"SSI_HighUtilSLRs",
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"RuntimeOptimized",
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"Quick",
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"Auto_1",
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"Auto_2",
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"Auto_3"
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]
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}
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},
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"POST_PLACE_POWER_OPT_DESIGN": {
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"IS_ENABLED": [
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"true"
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]
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},
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"PHYS_OPT_DESIGN": {
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"IS_ENABLED": [
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"true"
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],
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"ARGS": {
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"DIRECTIVE": [
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"Explore",
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"ExploreWithHoldFix",
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"ExploreWithAggressiveHoldFix",
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"AggressiveExplore",
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"AlternateReplication",
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"AggressiveFanoutOpt",
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"AddRetime",
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"AlternateFlowWithRetiming",
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"RuntimeOptimized"
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]
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}
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},
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"ROUTE_DESIGN": {
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"ARGS": {
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"DIRECTIVE": [
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"Explore",
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"AggressiveExplore",
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"NoTimingRelaxation",
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"MoreGlobalIterations",
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"HigherDelayCost",
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"RuntimeOptimized",
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"AlternateCLBRouting",
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"Quick"
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]
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}
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},
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"POST_ROUTE_PHYS_OPT_DESIGN": {
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"IS_ENABLED": [
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"true"
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],
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"ARGS": {
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"DIRECTIVE": [
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"Explore",
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"ExploreWithHoldFix",
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"ExploreWithAggressiveHoldFix",
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"AggressiveExplore",
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"AlternateReplication",
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"AggressiveFanoutOpt",
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"AddRetime",
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"AlternateFlowWithRetiming",
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"RuntimeOptimized"
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]
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}
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}
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}
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}
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}
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}
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}

‎hls4ml/templates/vitis_accelerator/accelerator_card.cfg

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@@ -7,19 +7,8 @@ prop=kernel.kernel_wrapper.kernel_flags=-std=c++11
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[hls]
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pre_tcl=./hls_config.tcl
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# hls-fpga-machine-learning clock control
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# hls-fpga-machine-learning kernel control
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[vivado]
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prop=run.impl_1.STEPS.OPT_DESIGN.IS_ENABLED=true
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prop=run.impl_1.STEPS.OPT_DESIGN.ARGS.DIRECTIVE=Explore
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prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=AltSpreadLogic_high
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prop=run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true
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prop=run.imp1_1.STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
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prop=run.impl_1.STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE=Explore
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prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true
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prop=run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE=AggressiveExplore
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# hls-fpga-machine-learning vivado directives

‎hls4ml/writer/vitis_accelerator_writer.py

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@@ -221,13 +221,18 @@ def write_accelerator_card_cfg(self, model):
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raise Exception(format(self.vitis_accelerator_config.get_platform()) +
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' has only ' + format(num_channels) + ' memory banks.')
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directives = self.vitis_accelerator_config.get_vivado_directives()
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for line in f.readlines():
225227
if 'MYPLATFORM' in line:
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newline = line.replace('MYPLATFORM', format(self.vitis_accelerator_config.get_platform()))
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elif "# hls-fpga-machine-learning clock control" in line:
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freq = round(1e9 / model.config.get_config_value('ClockPeriod'))
231+
newline = 'clock={}:kernel_wrapper\n'.format(freq)
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elif '# hls-fpga-machine-learning kernel control' in line:
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newline = '[connectivity]\n'
229234
newline += 'nk=kernel_wrapper:' + format(num_kernels) + '\n\n'
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if self.vitis_accelerator_config.get_board_type() == "alveo":
235+
if self.vitis_accelerator_config.get_board_type() == 'alveo':
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if memory_type == 'hbm':
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for i in range(0, num_kernels):
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newline += 'sp=kernel_wrapper_{}.in:HBM[{}:{}]\n'.format(i + 1, (i*2)*num_channels_per_cu, ((i*2 + 1)*num_channels_per_cu) - 1)
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newline += '\n'
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for i in range(0, num_kernels):
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newline += 'slr=kernel_wrapper_{}:SLR{}\n'.format(i + 1, i)
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elif '# hls-fpga-machine-learning vivado directives' in line:
248+
newline = ''
249+
if directives:
250+
newline += '[vivado]\n'
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for x in directives:
252+
newline += x + '\n'
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else:
243254
newline = line
244255
fout.write(newline)
245256
f.close()
246257
fout.close()
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# Copy hls_config.tcl
249-
filedir = os.path.dirname(os.path.abspath(__file__))
250-
srcpath = os.path.join(filedir, '../templates/vitis_accelerator/hls_config.tcl')
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dstpath = f'{model.config.get_output_dir()}/hls_config.tcl'
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copy(srcpath, dstpath)
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# Write hls_config.tcl
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tcl_f = open(os.path.join(filedir, '../templates/vitis_accelerator/hls_config.tcl'))
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tcl_fout = open(f'{model.config.get_output_dir()}/hls_config.tcl', 'w')
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for line in tcl_f.readlines():
263+
newline = line
264+
tcl_fout.write(newline)
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tcl_fout.write('\nset_clock_uncertainty {}\n'.format(model.config.get_config_value('ClockUncertainty', '12.5%')))
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tcl_f.close()
267+
tcl_fout.close()
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def write_nnet_utils_overrides(self, model):
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"""Override nnet_types.h pointer comparison

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