@@ -34,15 +34,44 @@ def _register_flows(self):
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self ._default_flow = register_flow ('ip' , None , requires = ip_flow_requirements , backend = self .name )
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def create_initial_config (
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- self , part = 'xcvu13p-flga2577-2-e' , clock_period = 5 , clock_uncertainty = '27%' , io_type = 'io_parallel' , ** _
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+ self ,
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+ part = 'xcvu13p-flga2577-2-e' ,
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+ clock_period = 5 ,
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+ clock_uncertainty = '27%' ,
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+ io_type = 'io_parallel' ,
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+ namespace = None ,
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+ write_weights_txt = False ,
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+ write_tar = True ,
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+ ** _ ,
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):
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+ """Create initial configuration of the Vitis backend.
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+
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+ Args:
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+ part (str, optional): The FPGA part to be used. Defaults to 'xcvu13p-flga2577-2-e'.
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+ clock_period (int, optional): The clock period. Defaults to 5.
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+ clock_uncertainty (str, optional): The clock uncertainty. Defaults to 27%.
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+ io_type (str, optional): Type of implementation used. One of
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+ 'io_parallel' or 'io_stream'. Defaults to 'io_parallel'.
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+ namespace (str, optional): If defined, place all generated code within a namespace. Defaults to None.
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+ write_weights_txt (bool, optional): If True, writes weights to .txt files which speeds up compilation.
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+ Defaults to False.
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+ write_tar (bool, optional): If True, compresses the output directory into a .tar.gz file. Defaults to True.
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+
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+ Returns:
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+ dict: initial configuration.
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+ """
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config = {}
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config ['Part' ] = part if part is not None else 'xcvu13p-flga2577-2-e'
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config ['ClockPeriod' ] = clock_period if clock_period is not None else 5
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config ['ClockUncertainty' ] = clock_uncertainty if clock_uncertainty is not None else '27%'
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config ['IOType' ] = io_type if io_type is not None else 'io_parallel'
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config ['HLSConfig' ] = {}
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+ config ['WriterConfig' ] = {
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+ 'Namespace' : namespace ,
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+ 'WriteWeightsTxt' : write_weights_txt ,
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+ 'WriteTar' : write_tar ,
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+ }
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return config
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