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alex-yang-upennQuentin Berthet
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fixing build() behavior + documentation
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docs/advanced/vitis_accelerator.rst

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -38,12 +38,12 @@ Build workflow
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At the call of the ``build`` method, the following option affect the build process:
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* ``reset``: TBD.
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* ``csim``: TBD.
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* ``synth``: TBD.
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* ``cosim``: TBD.
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* ``vsynth``: TBD.
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* ``debug``: TBD.
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* ``reset``: If True, clears files generated during previous build processes (STILL BEING TESTED).
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* ``csim``: If True, builds the project for Vitis' software emulation validation flow (STILL BEING TESTED)
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* ``synth``: If True, runs `make hls`, building object files for the kernel (STILL BEING TESTED)
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* ``cosim``: If True, builds the project for Vitis' hardware emulation validation flow (STILL BEING TESTED)
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* ``vsynth``: If True, runs `make xclbin`, building the .xclbin binary executable for the kernel (STILL BEING TESTED)
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* ``debug``: If True, compiles the c++ host code and the HLS in debug mode (STILL BEING TESTED)
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Once the project is generated, it possible to run manually the build steps by using one of the following ``make`` targets in the generated project directory:
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@@ -57,7 +57,7 @@ The generated host code application and the xclbin file can be executed as such:
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.. code-block:: Bash
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./host <myproject>.xclbin
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./host <build_directory>/<myproject>.xclbin
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Example
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=======
@@ -75,7 +75,9 @@ The following example is a modified version of `hsl4ml example 7 <https://github
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board='alveo-u55c',
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num_kernel=4,
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num_thread=8,
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batchsize=8192
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batchsize=8192,
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hw_quant=False,
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vivado_directives=["prop=run.impl_1.STEPS.PLACE_DESIGN.ARGS.DIRECTIVE=Explore"]
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)
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hls_model.compile()
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hls_model.build()
@@ -90,4 +92,4 @@ The generated host code application and the xclbin file can be executed as such:
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.. code-block:: Bash
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./host <myproject>.xclbin
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./host <build_directory>/<myproject>.xclbin

hls4ml/backends/vitis_accelerator/vitis_accelerator_backend.py

Lines changed: 19 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -81,33 +81,34 @@ def build(
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curr_dir = os.getcwd()
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os.chdir(model.config.get_output_dir())
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if cosim:
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target = "TARGET=hw_emu "
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elif csim:
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target = "TARGET=sw_emu "
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if reset:
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if vsynth:
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os.system("make cleanxclbin")
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if synth:
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os.system("make cleanhls")
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os.system("rm -rf host")
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if debug:
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target += "DEBUG"
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if vsynth:
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if synth:
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target = "all "
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process = "all "
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else:
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target = "xclbin "
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process = "xclbin "
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elif synth:
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target = "hls "
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process = "hls "
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else:
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target = "host "
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process = "host "
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if cosim:
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target += "TARGET=hw_emu "
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elif csim:
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target += "TARGET=sw_emu "
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if debug:
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target += "DEBUG"
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command = "make " + process + target
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command = "make " + target
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# Cleaning
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if reset:
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if vsynth:
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os.system("make cleanxclbin " + target)
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if synth:
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os.system("make cleanhls " + target)
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os.system("rm -rf host")
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# Pre-loading libudev
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ldconfig_output = subprocess.check_output(["ldconfig", "-p"]).decode("utf-8")

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