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Fix parsing of logic synthesis reports
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hls4ml/report/vivado_report.py

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -173,19 +173,23 @@ def parse_vivado_report(hls_dir):
173173
if os.path.isfile(vivado_syn_file):
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vivado_synth_rpt = {}
175175
with open(vivado_syn_file) as f:
176+
section = 0
176177
for line in f.readlines():
178+
match = re.match(r'^(\d)\.', line)
179+
if match:
180+
section = int(match.group(1))
177181
# Sometimes, phrases such as 'CLB Registers' can show up in the non-tabular sections of the report
178182
if '|' in line:
179-
if 'CLB LUTs' in line:
183+
if 'CLB LUTs' in line and section == 1:
180184
vivado_synth_rpt['LUT'] = line.split('|')[2].strip()
181-
elif 'CLB Registers' in line:
185+
elif 'CLB Registers' in line and section == 1:
182186
vivado_synth_rpt['FF'] = line.split('|')[2].strip()
183-
elif 'RAMB18 ' in line:
187+
elif 'Block RAM Tile' in line and section == 2:
184188
vivado_synth_rpt['BRAM_18K'] = line.split('|')[2].strip()
185-
elif 'DSPs' in line:
186-
vivado_synth_rpt['DSP48E'] = line.split('|')[2].strip()
187-
elif 'URAM' in line:
189+
elif 'URAM' in line and section == 2:
188190
vivado_synth_rpt['URAM'] = line.split('|')[2].strip()
191+
elif 'DSPs' in line and section == 3:
192+
vivado_synth_rpt['DSP48E'] = line.split('|')[2].strip()
189193
report['VivadoSynthReport'] = vivado_synth_rpt
190194
else:
191195
print('Vivado synthesis report not found.')

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