minor fixes and testing notebook

Author: alex-yang-upenn

hls4ml/templates/vitis_accelerator/Makefile

@@ -30,10 +30,10 @@ all: host kernel
 # Building kernel
 ./build/myproject_kernel.xo: kernel_wrapper.cpp
 	mkdir -p ./build
-	v++ -c -t hw --config ./u55c.cfg kernel_wrapper.cpp firmware/myproject.cpp -o ./build/myproject_kernel.xo $(KERN_LIBRARIES)
+	v++ -c -t hw --config ./accelerator_card.cfg kernel_wrapper.cpp firmware/myproject.cpp -o ./build/myproject_kernel.xo $(KERN_LIBRARIES)
 
 myproject_kernel.xclbin: ./build/myproject_kernel.xo
-	v++ -l -t hw --config ./u55c.cfg ./build/myproject_kernel.xo -o kernel_wrapper.xclbin
+	v++ -l -t hw --config ./accelerator_card.cfg ./build/myproject_kernel.xo -o kernel_wrapper.xclbin
 
 # Building Host 
 INCLUDES += -I$(XILINX_XRT)/include/ -I$(XILINX_VIVADO)/include/ -I$(XILINX_HLS)/include/ \

hls4ml/templates/vitis_accelerator/hls_config.tcl

@@ -1 +1,2 @@
-config_interface -m_axi_auto_max_ports=true
+config_interface -m_axi_auto_max_ports=true
+config_interface -m_axi_offset slave

hls4ml/templates/vitis_accelerator/libs/DdrFpga.hpp

@@ -0,0 +1,38 @@
+#pragma once
+
+#include "FpgaObj.hpp"
+
+template <class V, class W>
+class DdrFpga : public FpgaObj<V, W> {
+ public:
+    DdrFpga(int kernInputSize, int kernOutputSize, int numCU, int numThreads, int numEpochs)
+        : FpgaObj<V, W>(kernInputSize, kernOutputSize, numCU, numThreads, numEpochs) {
+    }
+
+    void allocateHostMemory(int chan_per_port) {
+        // Creating Buffer objects in Host memory
+        /* ***NOTE*** When creating a Buffer with user pointer (CL_MEM_USE_HOST_PTR), under the hood, user pointer
+        is used if it is properly aligned. when not aligned, runtime has no choice but to create
+        its own host side Buffer. So it is recommended to use this allocator if user wishes to
+        create Buffer using CL_MEM_USE_HOST_PTR to align user buffer to page boundary. It will 
+        ensure that user buffer is used when user creates Buffer/Mem object with CL_MEM_USE_HOST_PTR */
+        size_t vector_size_in_bytes = sizeof(V) * this->_kernInputSize;
+        size_t vector_size_out_bytes = sizeof(W) * this->_kernOutputSize;
+        for (int ib = 0; ib < this->_numThreads; ib++) {
+            for (int ik = 0; ik < this->_numCU; ik++) {
+                cl::Buffer buffer_in_tmp(this->context, 
+                        CL_MEM_USE_HOST_PTR | CL_MEM_READ_ONLY,
+                        vector_size_in_bytes,
+                        this->source_in.data() + ((ib*this->_numCU + ik) * this->_kernInputSize));
+                cl::Buffer buffer_out_tmp(this->context,
+                        CL_MEM_USE_HOST_PTR | CL_MEM_WRITE_ONLY,
+                        vector_size_out_bytes,
+                        this->source_hw_results.data() + ((ib*this->_numCU + ik) * this->_kernOutputSize));
+                this->buffer_in.push_back(buffer_in_tmp);
+                this->buffer_out.push_back(buffer_out_tmp);
+                this->krnl_xil[ib*this->_numCU + ik].setArg(0, this->buffer_in[ib*this->_numCU + ik]);
+                this->krnl_xil[ib*this->_numCU + ik].setArg(1, this->buffer_out[ib*this->_numCU + ik]);
+            }
+        }
+    }
+};

hls4ml/templates/vitis_accelerator/libs/HbmFpga.hpp

@@ -57,7 +57,7 @@ class HbmFpga : public FpgaObj<V, W> {
         size_t vector_size_out_bytes = sizeof(W) * this->_kernOutputSize;
         for (int ib = 0; ib < this->_numThreads; ib++) {
             for (int ik = 0; ik < this->_numCU; ik++) {
-                cl::Buffer buffer_in_tmp (this->context, 
+                cl::Buffer buffer_in_tmp(this->context, 
                         CL_MEM_USE_HOST_PTR | CL_MEM_EXT_PTR_XILINX | CL_MEM_READ_ONLY,
                         vector_size_in_bytes,
                         &(this->buf_in_ext[ib*this->_numCU + ik]));

hls4ml/templates/vitis_accelerator/myproject_host_cl.cpp

@@ -9,6 +9,7 @@
 #include "kernel_wrapper.h"
 #include "FpgaObj.hpp"
 #include "HbmFpga.hpp"
+#include "DdrFpga.hpp"
 #include "timing.hpp"
 #include "xcl2.hpp"
 
@@ -34,8 +35,7 @@ int main(int argc, char **argv) {
 
     std::vector<cl::Device> devices = xcl::get_xil_devices();  // Utility API that finds xilinx platforms and return a list of devices connected to Xilinx platforms
 
-    // Load xclbin
-    cl::Program::Binaries bins = xcl::import_binary_file(xclbinFilename);
+    cl::Program::Binaries bins = xcl::import_binary_file(xclbinFilename);  // Load xclbin
 
     fpga.initializeOpenCL(devices, bins);
 

hls4ml/writer/vitis_accelerator_writer.py

@@ -102,8 +102,8 @@ def write_kernel(self, model):
                             newline += '#define INSTREAMSIZE (BATCHSIZE * DATA_SIZE_IN)' + '\n\n'
                             newline += '#define DATA_SIZE_OUT ' + format(out.size_cpp()) + '\n'
                             newline += '#define OUTSTREAMSIZE (BATCHSIZE * DATA_SIZE_OUT)' + '\n\n'
-                            newline += 'typedef ' + format(inp.type.name) + ' in_buffer_t\n'
-                            newline += 'typedef ' + format(out.type.name) + ' out_buffer_t\n'
+                            newline += 'typedef ' + format(inp.type.name) + ' in_buffer_t;\n'
+                            newline += 'typedef ' + format(out.type.name) + ' out_buffer_t;\n'
                 elif io_type == 'io_stream':
                     for inp in model_inputs:
                         for out in model_outputs:
@@ -115,8 +115,8 @@ def write_kernel(self, model):
                             newline += '#define DATA_SIZE_OUT ' + format(out.size_cpp()) + '\n'
                             newline += '#define OUTSTREAMSIZE (BATCHSIZE * DATA_SIZE_OUT)' + '\n\n'
                             precision_str = model.config.backend.convert_precision_string(model.config.model_precision.get('default'))
-                            newline += 'typedef ' + precision_str + ' in_buffer_t\n'
-                            newline += 'typedef ' + precision_str + ' out_buffer_t\n'
+                            newline += 'typedef ' + precision_str + ' in_buffer_t;\n'
+                            newline += 'typedef ' + precision_str + ' out_buffer_t;\n'
             else:
                 newline = line
             fout_header.write(newline)