promoteToRegistersBelowThreads: extract depth from marker node

The thread mapping filters are now inserted right above
the band members that are mapped to thread identifiers,
while the marker node appears underneath.
The difference in schedule depth is therefore equal
to the number of thread identifiers mapped to a band member.

Once the mapping filter has been changed to explicitly keep
track of the thread identifiers mapped to band members,
this code can be further simplified.

The outermost thread mapping filter is returned because
findThreadMappingAncestor will be reused in isCoalesced,
where the result will also be used to derive the active
domain points outside the mapping.  In this case, it is
important to have a pointer to the outer mapping filter
in order to avoid the mapping filters getting mixed in.

Author: Sven Verdoolaege

tc/core/polyhedral/cuda/memory_promotion_heuristic.cc

@@ -298,6 +298,21 @@ size_t computeThreadIdxXScheduleDepth(
   return *depths.begin();
 }
 
+/*
+ * Return the outermost thread mapping filter among the ancestors of "node",
+ * assuming that there is at least one.
+ */
+const detail::ScheduleTree* findThreadMappingAncestor(
+    const detail::ScheduleTree* root,
+    const detail::ScheduleTree* node) {
+  auto ancestors = node->ancestors(root);
+  ancestors = functional::Filter(isThreadMapping, ancestors);
+  if (ancestors.size() < 1) {
+    throw promotion::PromotionLogicError("missing MappingFilter");
+  }
+  return ancestors[0];
+}
+
 /*
  * Check if a reference group is accessed in a coalesced way.
  *
@@ -595,32 +610,17 @@ void promoteToRegistersBelowThreads(Scop& scop, size_t nRegisters) {
     auto markers = findThreadSpecificMarkers(root);
 
     for (auto marker : markers) {
-      // Find out how many threads are actually mapped.  Active domain points
-      // will involve all mapping parameters when we take them below the
-      // mapping.  Skip mapping parameters obviously mapped to 0, because they
-      // do not correspond to band members that should be fixed to obtain
-      // per-thread-group access relations.
-      auto points = activeDomainPoints(root, marker);
       auto partialSched = prefixSchedule(root, marker);
       // Pure affine schedule without (mapping) filters.
       auto partialSchedMupa = prefixScheduleMupa(root, marker);
 
       auto depth = marker->scheduleDepth(root);
-      size_t nMappedThreads = 0;
-      for (unsigned j = 0; j < points.dim(isl::dim_type::param); ++j) {
-        auto id = points.get_space().get_dim_id(isl::dim_type::param, j);
-        for (size_t i = 0; i < mapping::ThreadId::kMaxDim; ++i) {
-          if (id != mapping::ThreadId::makeId(i)) {
-            continue;
-          }
-          if (isl::getParamValIfFixed(points, j) ==
-              isl::val::zero(points.get_ctx())) {
-            continue;
-          }
-          ++nMappedThreads;
-          break;
-        }
-      }
+
+      // Thread mapping filters are inserted immediately above the members
+      // mapped to threads.  The number of intermediate band members
+      // is therefore equal to the number of mapped thread identifiers.
+      auto mapping = findThreadMappingAncestor(root, marker);
+      size_t nMappedThreads = marker->scheduleDepth(mapping);
 
       auto groupMap = TensorReferenceGroup::accessedBySubtree(marker, scop);
       for (auto& tensorGroups : groupMap) {

tc/external/detail/islpp.h

@@ -395,21 +395,6 @@ auto end(L& list) -> ListIter<decltype(list.get(0)), L> {
 using detail::begin;
 using detail::end;
 
-template <typename T>
-isl::val getParamValIfFixed(T t, int pos) {
-  auto val = isl::val::nan(t.get_ctx());
-  for (auto set : isl::UnionAsVector<T>(t)) {
-    auto currentVal = set.plain_get_val_if_fixed(isl::dim_type::param, pos);
-    if (currentVal.is_nan()) {
-      return currentVal;
-    }
-    if (!val.is_nan() && val != currentVal) {
-      return isl::val::nan(t.get_ctx());
-    }
-    val = currentVal;
-  }
-  return val;
-}
 } // namespace isl
 
 namespace isl {