Explore the PIE capabilities on the ESP32-P4 · Espressif Developer Portal

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Explore the PIE capabilities on the ESP32-P4 · Espressif Developer Portal

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https://developer.espressif.com/blog/2024/12/pie-introduction/

[Emill]

Has the *.QUP variant for all the *.VMULAS.* instructions been removed in ESP32-P4 that was present in ESP32-S3? It was really useful...

[YanKE01]

From the current datasheet,the *.QUP variant for all the .VMULAS. instructions has indeed disappeared.

[BoumedineBillal]

Could you provide details about the PIE and XHWLP documentation (ESP32-P4 TRM or datasheet)? Specifically, I'm looking for information on how these features

[YanKE01]

The TRM for ESP32-P4 is not fully ready yet and will require some more time.

[razor7788]

The TRM for ESP32-P4 is not fully ready yet and will require some more time.

Is there any update news aboout TRM for ESP32-P4?

[YanKE01]

The TRM for the ESP32-P4 is still not publicly available. If you wish to obtain it, you may try contacting Espressif's technical support through official website.

[BitsForPeople]

In the inline assembly example, the employed 'manual' way to allocate registers and save them on the stack should not be done. The way it is now, it's somewhat inefficient, and, more importantly, may result in corruption/incorrect operation, e.g. if the compiler decides to (inline the add_pie() function and) provide "y" in register x31 to the assembly fragment (i.e. %1 = x31).

The better approach is to let the compiler handle the allocation of the (non-Q) registers, like

void add_pie(int16_t *x, int16_t *y, int16_t *z, int n)
{
    int i = 0;
    asm volatile(
        "loop:\n"
        " beq %[i], %[n], exit \n"
        " esp.vld.128.ip q0, %[x], 16 \n"
        " esp.vld.128.ip q1, %[x], 16 \n"
        " esp.vld.128.ip q2, %[x], 16 \n"
        " esp.vld.128.ip q3, %[x], 16 \n"
		
        " esp.vld.128.ip q4, %[y], 16 \n"
        " esp.vld.128.ip q5, %[y], 16 \n"
        " esp.vld.128.ip q6, %[y], 16 \n"
        " esp.vld.128.ip q7, %[y], 16 \n"

        " esp.vadd.s16 q0, q0, q4 \n"
        " esp.vadd.s16 q1, q1, q5 \n"
        " esp.vadd.s16 q2, q2, q6 \n"
        " esp.vadd.s16 q3, q3, q7 \n"

        " esp.vst.128.ip q0, %[z], 16 \n"
        " esp.vst.128.ip q1, %[z], 16 \n"
        " esp.vst.128.ip q2, %[z], 16 \n"
        " esp.vst.128.ip q3, %[z], 16 \n"

        " addi %[i], %[i], 32 \n"
        " j loop \n"
        "exit:\n"
        : [x] "+&r" (x), [y] "+&r" (y) , [z] "+&r" (z), [i] "+&r" (i)
		: "r" (n)    
    );
}