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mshockwavemshockwave
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[RISCV] Mark RVV stores and segmented loads as masked pseudo (llvm#123106)
So that we can turn masked operations with all-ones masks into their unmasked counterpart. Note: loads other than segmented ones had been marked as masked.
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8 files changed

+391
-2
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1932,6 +1932,7 @@ multiclass VPseudoUSStore {
19321932
def "E" # eew # "_V_" # LInfo : VPseudoUSStoreNoMask<vreg, eew>,
19331933
VSESched<LInfo>;
19341934
def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSStoreMask<vreg, eew>,
1935+
RISCVMaskedPseudo<MaskIdx=2>,
19351936
VSESched<LInfo>;
19361937
}
19371938
}
@@ -1958,6 +1959,7 @@ multiclass VPseudoSStore {
19581959
def "E" # eew # "_V_" # LInfo : VPseudoSStoreNoMask<vreg, eew>,
19591960
VSSSched<eew, LInfo>;
19601961
def "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSStoreMask<vreg, eew>,
1962+
RISCVMaskedPseudo<MaskIdx=3>,
19611963
VSSSched<eew, LInfo>;
19621964
}
19631965
}
@@ -1984,6 +1986,7 @@ multiclass VPseudoIStore<bit Ordered> {
19841986
VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
19851987
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
19861988
VPseudoIStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered>,
1989+
RISCVMaskedPseudo<MaskIdx=3>,
19871990
VSXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
19881991
}
19891992
}
@@ -3709,7 +3712,8 @@ multiclass VPseudoUSSegLoad {
37093712
def nf # "E" # eew # "_V_" # LInfo :
37103713
VPseudoUSSegLoadNoMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
37113714
def nf # "E" # eew # "_V_" # LInfo # "_MASK" :
3712-
VPseudoUSSegLoadMask<vreg, eew, nf>, VLSEGSched<nf, eew, LInfo>;
3715+
VPseudoUSSegLoadMask<vreg, eew, nf>, RISCVMaskedPseudo<MaskIdx=2>,
3716+
VLSEGSched<nf, eew, LInfo>;
37133717
}
37143718
}
37153719
}
@@ -3726,7 +3730,8 @@ multiclass VPseudoUSSegLoadFF {
37263730
def nf # "E" # eew # "FF_V_" # LInfo :
37273731
VPseudoUSSegLoadFFNoMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
37283732
def nf # "E" # eew # "FF_V_" # LInfo # "_MASK" :
3729-
VPseudoUSSegLoadFFMask<vreg, eew, nf>, VLSEGFFSched<nf, eew, LInfo>;
3733+
VPseudoUSSegLoadFFMask<vreg, eew, nf>, RISCVMaskedPseudo<MaskIdx=2>,
3734+
VLSEGFFSched<nf, eew, LInfo>;
37303735
}
37313736
}
37323737
}
@@ -3743,6 +3748,7 @@ multiclass VPseudoSSegLoad {
37433748
def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask<vreg, eew, nf>,
37443749
VLSSEGSched<nf, eew, LInfo>;
37453750
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegLoadMask<vreg, eew, nf>,
3751+
RISCVMaskedPseudo<MaskIdx=3>,
37463752
VLSSEGSched<nf, eew, LInfo>;
37473753
}
37483754
}
@@ -3773,6 +3779,7 @@ multiclass VPseudoISegLoad<bit Ordered> {
37733779
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
37743780
VPseudoISegLoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
37753781
nf, Ordered>,
3782+
RISCVMaskedPseudo<MaskIdx=3>,
37763783
VLXSEGSched<nf, dataEEW, Ordered, DataLInfo>;
37773784
}
37783785
}
@@ -3792,6 +3799,7 @@ multiclass VPseudoUSSegStore {
37923799
def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask<vreg, eew, nf>,
37933800
VSSEGSched<nf, eew, LInfo>;
37943801
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask<vreg, eew, nf>,
3802+
RISCVMaskedPseudo<MaskIdx=2>,
37953803
VSSEGSched<nf, eew, LInfo>;
37963804
}
37973805
}
@@ -3809,6 +3817,7 @@ multiclass VPseudoSSegStore {
38093817
def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew, nf>,
38103818
VSSSEGSched<nf, eew, LInfo>;
38113819
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew, nf>,
3820+
RISCVMaskedPseudo<MaskIdx=3>,
38123821
VSSSEGSched<nf, eew, LInfo>;
38133822
}
38143823
}
@@ -3839,6 +3848,7 @@ multiclass VPseudoISegStore<bit Ordered> {
38393848
def nf # "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
38403849
VPseudoISegStoreMask<Vreg, IdxVreg, idxEEW, idxEMUL.value,
38413850
nf, Ordered>,
3851+
RISCVMaskedPseudo<MaskIdx=3>,
38423852
VSXSEGSched<nf, idxEEW, Ordered, DataLInfo>;
38433853
}
38443854
}

‎llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,18 @@ entry:
2929
ret <vscale x 1 x i8> %1
3030
}
3131

32+
define <vscale x 1 x i8> @test_vlseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t(ptr %base, i64 %vl) {
33+
; CHECK-LABEL: test_vlseg2_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_2t:
34+
; CHECK: # %bb.0: # %entry
35+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
36+
; CHECK-NEXT: vlseg2e8.v v7, (a0)
37+
; CHECK-NEXT: ret
38+
entry:
39+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv1i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
40+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_2t(target("riscv.vector.tuple", <vscale x 1 x i8>, 2) %0, i32 1)
41+
ret <vscale x 1 x i8> %1
42+
}
43+
3244
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv2i8_2t(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, i64, i64)
3345
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv2i8_2t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 2), ptr, <vscale x 2 x i1>, i64, i64, i64)
3446

@@ -191,6 +203,18 @@ entry:
191203
ret <vscale x 1 x i8> %1
192204
}
193205

206+
define <vscale x 1 x i8> @test_vlseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
207+
; CHECK-LABEL: test_vlseg3_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_3t:
208+
; CHECK: # %bb.0: # %entry
209+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
210+
; CHECK-NEXT: vlseg3e8.v v7, (a0)
211+
; CHECK-NEXT: ret
212+
entry:
213+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
214+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_3t(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, i32 1)
215+
ret <vscale x 1 x i8> %1
216+
}
217+
194218
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv2i8_3t(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, i64, i64)
195219
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv2i8_3t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 3), ptr, <vscale x 2 x i1>, i64, i64, i64)
196220

@@ -326,6 +350,18 @@ entry:
326350
ret <vscale x 1 x i8> %1
327351
}
328352

353+
define <vscale x 1 x i8> @test_vlseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
354+
; CHECK-LABEL: test_vlseg4_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_4t:
355+
; CHECK: # %bb.0: # %entry
356+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
357+
; CHECK-NEXT: vlseg4e8.v v7, (a0)
358+
; CHECK-NEXT: ret
359+
entry:
360+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv1i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
361+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_4t(target("riscv.vector.tuple", <vscale x 1 x i8>, 4) %0, i32 1)
362+
ret <vscale x 1 x i8> %1
363+
}
364+
329365
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv2i8_4t(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, i64, i64)
330366
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv2i8_4t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 4), ptr, <vscale x 2 x i1>, i64, i64, i64)
331367

@@ -461,6 +497,18 @@ entry:
461497
ret <vscale x 1 x i8> %1
462498
}
463499

500+
define <vscale x 1 x i8> @test_vlseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
501+
; CHECK-LABEL: test_vlseg5_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_5t:
502+
; CHECK: # %bb.0: # %entry
503+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
504+
; CHECK-NEXT: vlseg5e8.v v7, (a0)
505+
; CHECK-NEXT: ret
506+
entry:
507+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv1i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
508+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_5t(target("riscv.vector.tuple", <vscale x 1 x i8>, 5) %0, i32 1)
509+
ret <vscale x 1 x i8> %1
510+
}
511+
464512
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv2i8_5t(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, i64, i64)
465513
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv2i8_5t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 5), ptr, <vscale x 2 x i1>, i64, i64, i64)
466514

@@ -569,6 +617,18 @@ entry:
569617
ret <vscale x 1 x i8> %1
570618
}
571619

620+
define <vscale x 1 x i8> @test_vlseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
621+
; CHECK-LABEL: test_vlseg6_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_6t:
622+
; CHECK: # %bb.0: # %entry
623+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
624+
; CHECK-NEXT: vlseg6e8.v v7, (a0)
625+
; CHECK-NEXT: ret
626+
entry:
627+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv1i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
628+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_6t(target("riscv.vector.tuple", <vscale x 1 x i8>, 6) %0, i32 1)
629+
ret <vscale x 1 x i8> %1
630+
}
631+
572632
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv2i8_6t(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, i64, i64)
573633
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv2i8_6t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 6), ptr, <vscale x 2 x i1>, i64, i64, i64)
574634

@@ -677,6 +737,18 @@ entry:
677737
ret <vscale x 1 x i8> %1
678738
}
679739

740+
define <vscale x 1 x i8> @test_vlseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
741+
; CHECK-LABEL: test_vlseg7_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_7t:
742+
; CHECK: # %bb.0: # %entry
743+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
744+
; CHECK-NEXT: vlseg7e8.v v7, (a0)
745+
; CHECK-NEXT: ret
746+
entry:
747+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv1i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
748+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_7t(target("riscv.vector.tuple", <vscale x 1 x i8>, 7) %0, i32 1)
749+
ret <vscale x 1 x i8> %1
750+
}
751+
680752
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv2i8_7t(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, i64, i64)
681753
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv2i8_7t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 7), ptr, <vscale x 2 x i1>, i64, i64, i64)
682754

@@ -785,6 +857,18 @@ entry:
785857
ret <vscale x 1 x i8> %1
786858
}
787859

860+
define <vscale x 1 x i8> @test_vlseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) {
861+
; CHECK-LABEL: test_vlseg8_allonesmask_nxv1i8_triscv.vector.tuple_nxv1i8_8t:
862+
; CHECK: # %bb.0: # %entry
863+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
864+
; CHECK-NEXT: vlseg8e8.v v7, (a0)
865+
; CHECK-NEXT: ret
866+
entry:
867+
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv1i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) undef, ptr %base, <vscale x 1 x i1> splat (i1 true), i64 %vl, i64 1, i64 3)
868+
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_8t(target("riscv.vector.tuple", <vscale x 1 x i8>, 8) %0, i32 1)
869+
ret <vscale x 1 x i8> %1
870+
}
871+
788872
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv2i8_8t(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, i64, i64)
789873
declare target("riscv.vector.tuple", <vscale x 2 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv2i8_8t.nxv2i1(target("riscv.vector.tuple", <vscale x 2 x i8>, 8), ptr, <vscale x 2 x i1>, i64, i64, i64)
790874

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