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[Xtensa] Implement volatile load/store. (llvm#110292)
Add a memory wait "MEMW" instruction before volatile load/store operations, as implemented in GCC.
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4 files changed

+207
-15
lines changed

4 files changed

+207
-15
lines changed

‎llvm/lib/Target/Xtensa/XtensaISelLowering.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
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#include "XtensaISelLowering.h"
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#include "XtensaConstantPoolValue.h"
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#include "XtensaInstrInfo.h"
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#include "XtensaSubtarget.h"
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#include "XtensaTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
@@ -1104,10 +1105,26 @@ XtensaTargetLowering::emitSelectCC(MachineInstr &MI,
11041105
MachineBasicBlock *XtensaTargetLowering::EmitInstrWithCustomInserter(
11051106
MachineInstr &MI, MachineBasicBlock *MBB) const {
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DebugLoc DL = MI.getDebugLoc();
1108+
const XtensaInstrInfo &TII = *Subtarget.getInstrInfo();
11071109

11081110
switch (MI.getOpcode()) {
11091111
case Xtensa::SELECT:
11101112
return emitSelectCC(MI, MBB);
1113+
case Xtensa::S8I:
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case Xtensa::S16I:
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case Xtensa::S32I:
1116+
case Xtensa::L8UI:
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case Xtensa::L16SI:
1118+
case Xtensa::L16UI:
1119+
case Xtensa::L32I: {
1120+
// Insert memory wait instruction "memw" before volatile load/store as it is
1121+
// implemented in gcc. If memoperands is empty then assume that it aslo
1122+
// maybe volatile load/store and insert "memw".
1123+
if (MI.memoperands_empty() || (*MI.memoperands_begin())->isVolatile()) {
1124+
BuildMI(*MBB, MI, DL, TII.get(Xtensa::MEMW));
1125+
}
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return MBB;
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}
11111128
default:
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llvm_unreachable("Unexpected instr type to insert");
11131130
}

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ def SSAI : RRR_Inst<0x00, 0x00, 0x04, (outs), (ins uimm5:$imm),
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//===----------------------------------------------------------------------===//
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// Load instructions
198-
let mayLoad = 1 in {
198+
let mayLoad = 1, usesCustomInserter = 1 in {
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200200
class Load_RRI8<bits<4> oper, string instrAsm, SDPatternOperator opNode,
201201
ComplexPattern addrOp, Operand memOp>
@@ -216,7 +216,7 @@ def L16UI : Load_RRI8<0x01, "l16ui", zextloadi16, addr_ish2, mem16>;
216216
def L32I : Load_RRI8<0x02, "l32i", load, addr_ish4, mem32>;
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218218
// Store instructions
219-
let mayStore = 1 in {
219+
let mayStore = 1, usesCustomInserter = 1 in {
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class Store_II8<bits<4> oper, string instrAsm, SDPatternOperator opNode,
221221
ComplexPattern addrOp, Operand memOp>
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: RRI8_Inst<0x02, (outs), (ins AR:$t, memOp:$addr),

‎llvm/test/CodeGen/Xtensa/blockaddress.ll

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,21 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc --mtriple=xtensa < %s | FileCheck %s
23

34
@addr = global ptr null
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56
define void @test_blockaddress() {
6-
7-
store volatile ptr blockaddress(@test_blockaddress, %block), ptr @addr
8-
; CHECK: .literal_position
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; CHECK-NEXT: .literal .LCPI0_0, addr
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; CHECK-NEXT: .literal .LCPI0_1, .Ltmp0
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; CHECK-LABEL: test_blockaddress:
12-
; CHECK: # %bb.0:
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; CHECK-NEXT: l32r a8, .LCPI0_0
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; CHECK-NEXT: l32r a9, .LCPI0_1
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; CHECK-NEXT: s32i a9, a8, 0
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; CHECK-NEXT: l32i a8, a8, 0
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; CHECK-NEXT: jx a8
18-
; CHECK-NEXT: .Ltmp0:
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; CHECK-NEXT: .LBB0_1:
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; CHECK: l32r a8, .LCPI0_0
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; CHECK-NEXT: l32r a9, .LCPI0_1
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; CHECK-NEXT: memw
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; CHECK-NEXT: s32i a9, a8, 0
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; CHECK-NEXT: memw
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; CHECK-NEXT: l32i a8, a8, 0
14+
; CHECK-NEXT: jx a8
15+
; CHECK-NEXT: .Ltmp0: # Block address taken
16+
; CHECK-NEXT: .LBB0_1: # %block
17+
; CHECK-NEXT: ret
18+
store volatile ptr blockaddress(@test_blockaddress, %block), ptr @addr
2019

2120
%val = load volatile ptr, ptr @addr
2221
indirectbr ptr %val, [label %block]

‎llvm/test/CodeGen/Xtensa/volatile.ll

Lines changed: 176 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,176 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \
3+
; RUN: | FileCheck %s
4+
5+
@x_i8 = common dso_local global i8 0, align 8
6+
@y_i8 = common dso_local global i8 0, align 8
7+
@x_i16 = common dso_local global i16 0, align 8
8+
@y_i16 = common dso_local global i16 0, align 8
9+
@x_i32 = common dso_local global i32 0, align 8
10+
@y_i32 = common dso_local global i32 0, align 8
11+
@x_i64 = common dso_local global i64 0, align 8
12+
@y_i64 = common dso_local global i64 0, align 8
13+
@x_float = common dso_local global float 0.0, align 8
14+
@y_float = common dso_local global float 0.0, align 8
15+
@x_double = common dso_local global double 0.0, align 8
16+
@y_double = common dso_local global double 0.0, align 8
17+
@x_vec = common dso_local global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 8
18+
@y_vec = common dso_local global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 8
19+
20+
define void @test() {
21+
; CHECK-LABEL: test:
22+
; CHECK: l32r a8, .LCPI0_0
23+
; CHECK-NEXT: memw
24+
; CHECK-NEXT: l8ui a8, a8, 0
25+
; CHECK-NEXT: l32r a9, .LCPI0_1
26+
; CHECK-NEXT: memw
27+
; CHECK-NEXT: s8i a8, a9, 0
28+
; CHECK-NEXT: l32r a8, .LCPI0_2
29+
; CHECK-NEXT: memw
30+
; CHECK-NEXT: l16ui a8, a8, 0
31+
; CHECK-NEXT: l32r a9, .LCPI0_3
32+
; CHECK-NEXT: memw
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; CHECK-NEXT: s16i a8, a9, 0
34+
; CHECK-NEXT: l32r a8, .LCPI0_4
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; CHECK-NEXT: memw
36+
; CHECK-NEXT: l32i a8, a8, 0
37+
; CHECK-NEXT: l32r a9, .LCPI0_5
38+
; CHECK-NEXT: memw
39+
; CHECK-NEXT: s32i a8, a9, 0
40+
; CHECK-NEXT: ret
41+
42+
entry:
43+
%a = load volatile i8, ptr @x_i8, align 4
44+
store volatile i8 %a, ptr @y_i8, align 4
45+
%b = load volatile i16, ptr @x_i16, align 4
46+
store volatile i16 %b, ptr @y_i16, align 4
47+
%c = load volatile i32, ptr @x_i32, align 4
48+
store volatile i32 %c, ptr @y_i32, align 4
49+
ret void
50+
}
51+
52+
53+
define void @test_i8() {
54+
; CHECK-LABEL: test_i8:
55+
; CHECK: l32r a8, .LCPI1_0
56+
; CHECK-NEXT: memw
57+
; CHECK-NEXT: l8ui a8, a8, 0
58+
; CHECK-NEXT: l32r a9, .LCPI1_1
59+
; CHECK-NEXT: memw
60+
; CHECK-NEXT: s8i a8, a9, 0
61+
; CHECK-NEXT: ret
62+
entry:
63+
%a = load volatile i8, ptr @x_i8, align 4
64+
store volatile i8 %a, ptr @y_i8, align 4
65+
ret void
66+
}
67+
68+
define void @test_i16() {
69+
; CHECK-LABEL: test_i16:
70+
; CHECK: l32r a8, .LCPI2_0
71+
; CHECK-NEXT: memw
72+
; CHECK-NEXT: l16ui a8, a8, 0
73+
; CHECK-NEXT: l32r a9, .LCPI2_1
74+
; CHECK-NEXT: memw
75+
; CHECK-NEXT: s16i a8, a9, 0
76+
; CHECK-NEXT: ret
77+
entry:
78+
%a = load volatile i16, ptr @x_i16, align 4
79+
store volatile i16 %a, ptr @y_i16, align 4
80+
ret void
81+
}
82+
83+
define void @test_i32() {
84+
; CHECK-LABEL: test_i32:
85+
; CHECK: l32r a8, .LCPI3_0
86+
; CHECK-NEXT: memw
87+
; CHECK-NEXT: l32i a8, a8, 0
88+
; CHECK-NEXT: l32r a9, .LCPI3_1
89+
; CHECK-NEXT: memw
90+
; CHECK-NEXT: s32i a8, a9, 0
91+
; CHECK-NEXT: ret
92+
entry:
93+
%a = load volatile i32, ptr @x_i32, align 4
94+
store volatile i32 %a, ptr @y_i32, align 4
95+
ret void
96+
}
97+
98+
define void @test_i64() {
99+
; CHECK-LABEL: test_i64:
100+
; CHECK: l32r a8, .LCPI4_0
101+
; CHECK-NEXT: memw
102+
; CHECK-NEXT: l32i a9, a8, 0
103+
; CHECK-NEXT: memw
104+
; CHECK-NEXT: l32i a8, a8, 4
105+
; CHECK-NEXT: l32r a10, .LCPI4_1
106+
; CHECK-NEXT: memw
107+
; CHECK-NEXT: s32i a8, a10, 4
108+
; CHECK-NEXT: memw
109+
; CHECK-NEXT: s32i a9, a10, 0
110+
; CHECK-NEXT: ret
111+
entry:
112+
%a = load volatile i64, ptr @x_i64, align 4
113+
store volatile i64 %a, ptr @y_i64, align 4
114+
ret void
115+
}
116+
117+
define void @test_float() {
118+
; CHECK-LABEL: test_float:
119+
; CHECK: l32r a8, .LCPI5_0
120+
; CHECK-NEXT: memw
121+
; CHECK-NEXT: l32i a8, a8, 0
122+
; CHECK-NEXT: l32r a9, .LCPI5_1
123+
; CHECK-NEXT: memw
124+
; CHECK-NEXT: s32i a8, a9, 0
125+
; CHECK-NEXT: ret
126+
entry:
127+
%a = load volatile float, ptr @x_float, align 4
128+
store volatile float %a, ptr @y_float, align 4
129+
ret void
130+
}
131+
132+
define void @test_double() {
133+
; CHECK-LABEL: test_double:
134+
; CHECK: l32r a8, .LCPI6_0
135+
; CHECK-NEXT: memw
136+
; CHECK-NEXT: l32i a9, a8, 0
137+
; CHECK-NEXT: memw
138+
; CHECK-NEXT: l32i a8, a8, 4
139+
; CHECK-NEXT: l32r a10, .LCPI6_1
140+
; CHECK-NEXT: memw
141+
; CHECK-NEXT: s32i a8, a10, 4
142+
; CHECK-NEXT: memw
143+
; CHECK-NEXT: s32i a9, a10, 0
144+
; CHECK-NEXT: ret
145+
entry:
146+
%a = load volatile double, ptr @x_double, align 4
147+
store volatile double %a, ptr @y_double, align 4
148+
ret void
149+
}
150+
151+
define void @test_vec() {
152+
; CHECK-LABEL: test_vec:
153+
; CHECK: l32r a8, .LCPI7_0
154+
; CHECK-NEXT: memw
155+
; CHECK-NEXT: l32i a9, a8, 0
156+
; CHECK-NEXT: memw
157+
; CHECK-NEXT: l32i a10, a8, 4
158+
; CHECK-NEXT: memw
159+
; CHECK-NEXT: l32i a11, a8, 8
160+
; CHECK-NEXT: memw
161+
; CHECK-NEXT: l32i a8, a8, 12
162+
; CHECK-NEXT: l32r a7, .LCPI7_1
163+
; CHECK-NEXT: memw
164+
; CHECK-NEXT: s32i a8, a7, 12
165+
; CHECK-NEXT: memw
166+
; CHECK-NEXT: s32i a11, a7, 8
167+
; CHECK-NEXT: memw
168+
; CHECK-NEXT: s32i a10, a7, 4
169+
; CHECK-NEXT: memw
170+
; CHECK-NEXT: s32i a9, a7, 0
171+
; CHECK-NEXT: ret
172+
entry:
173+
%a = load volatile <4 x i32>, ptr @x_vec, align 4
174+
store volatile <4 x i32> %a, ptr @y_vec, align 4
175+
ret void
176+
}

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