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| 1 | +//===-- SPIRVPostLegalizer.cpp - ammend info after legalization -*- C++ -*-===// |
| 2 | +// |
| 3 | +// which may appear after the legalizer pass |
| 4 | +// |
| 5 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 6 | +// See https://llvm.org/LICENSE.txt for license information. |
| 7 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 8 | +// |
| 9 | +//===----------------------------------------------------------------------===// |
| 10 | +// |
| 11 | +// The pass partially apply pre-legalization logic to new instructions inserted |
| 12 | +// as a result of legalization: |
| 13 | +// - assigns SPIR-V types to registers for new instructions. |
| 14 | +// |
| 15 | +//===----------------------------------------------------------------------===// |
| 16 | + |
| 17 | +#include "SPIRV.h" |
| 18 | +#include "SPIRVSubtarget.h" |
| 19 | +#include "SPIRVUtils.h" |
| 20 | +#include "llvm/ADT/PostOrderIterator.h" |
| 21 | +#include "llvm/Analysis/OptimizationRemarkEmitter.h" |
| 22 | +#include "llvm/IR/Attributes.h" |
| 23 | +#include "llvm/IR/Constants.h" |
| 24 | +#include "llvm/IR/DebugInfoMetadata.h" |
| 25 | +#include "llvm/IR/IntrinsicsSPIRV.h" |
| 26 | +#include "llvm/Target/TargetIntrinsicInfo.h" |
| 27 | + |
| 28 | +#define DEBUG_TYPE "spirv-postlegalizer" |
| 29 | + |
| 30 | +using namespace llvm; |
| 31 | + |
| 32 | +namespace { |
| 33 | +class SPIRVPostLegalizer : public MachineFunctionPass { |
| 34 | +public: |
| 35 | + static char ID; |
| 36 | + SPIRVPostLegalizer() : MachineFunctionPass(ID) { |
| 37 | + initializeSPIRVPostLegalizerPass(*PassRegistry::getPassRegistry()); |
| 38 | + } |
| 39 | + bool runOnMachineFunction(MachineFunction &MF) override; |
| 40 | +}; |
| 41 | +} // namespace |
| 42 | + |
| 43 | +// Defined in SPIRVLegalizerInfo.cpp. |
| 44 | +extern bool isTypeFoldingSupported(unsigned Opcode); |
| 45 | + |
| 46 | +namespace llvm { |
| 47 | +// Defined in SPIRVPreLegalizer.cpp. |
| 48 | +extern Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpirvTy, |
| 49 | + SPIRVGlobalRegistry *GR, |
| 50 | + MachineIRBuilder &MIB, |
| 51 | + MachineRegisterInfo &MRI); |
| 52 | +extern void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, |
| 53 | + MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR); |
| 54 | +} // namespace llvm |
| 55 | + |
| 56 | +static bool isMetaInstrGET(unsigned Opcode) { |
| 57 | + return Opcode == SPIRV::GET_ID || Opcode == SPIRV::GET_fID || |
| 58 | + Opcode == SPIRV::GET_pID || Opcode == SPIRV::GET_vID || |
| 59 | + Opcode == SPIRV::GET_vfID; |
| 60 | +} |
| 61 | + |
| 62 | +static bool mayBeInserted(unsigned Opcode) { |
| 63 | + switch (Opcode) { |
| 64 | + case TargetOpcode::G_SMAX: |
| 65 | + case TargetOpcode::G_UMAX: |
| 66 | + case TargetOpcode::G_SMIN: |
| 67 | + case TargetOpcode::G_UMIN: |
| 68 | + case TargetOpcode::G_FMINNUM: |
| 69 | + case TargetOpcode::G_FMINIMUM: |
| 70 | + case TargetOpcode::G_FMAXNUM: |
| 71 | + case TargetOpcode::G_FMAXIMUM: |
| 72 | + return true; |
| 73 | + default: |
| 74 | + return isTypeFoldingSupported(Opcode); |
| 75 | + } |
| 76 | +} |
| 77 | + |
| 78 | +static void processNewInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, |
| 79 | + MachineIRBuilder MIB) { |
| 80 | + MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 81 | + |
| 82 | + for (MachineBasicBlock &MBB : MF) { |
| 83 | + for (MachineInstr &I : MBB) { |
| 84 | + const unsigned Opcode = I.getOpcode(); |
| 85 | + if (Opcode == TargetOpcode::G_UNMERGE_VALUES) { |
| 86 | + unsigned ArgI = I.getNumOperands() - 1; |
| 87 | + Register SrcReg = I.getOperand(ArgI).isReg() |
| 88 | + ? I.getOperand(ArgI).getReg() |
| 89 | + : Register(0); |
| 90 | + SPIRVType *DefType = |
| 91 | + SrcReg.isValid() ? GR->getSPIRVTypeForVReg(SrcReg) : nullptr; |
| 92 | + if (!DefType || DefType->getOpcode() != SPIRV::OpTypeVector) |
| 93 | + report_fatal_error( |
| 94 | + "cannot select G_UNMERGE_VALUES with a non-vector argument"); |
| 95 | + SPIRVType *ScalarType = |
| 96 | + GR->getSPIRVTypeForVReg(DefType->getOperand(1).getReg()); |
| 97 | + for (unsigned i = 0; i < I.getNumDefs(); ++i) { |
| 98 | + Register ResVReg = I.getOperand(i).getReg(); |
| 99 | + SPIRVType *ResType = GR->getSPIRVTypeForVReg(ResVReg); |
| 100 | + if (!ResType) { |
| 101 | + // There was no "assign type" actions, let's fix this now |
| 102 | + ResType = ScalarType; |
| 103 | + MRI.setRegClass(ResVReg, &SPIRV::IDRegClass); |
| 104 | + MRI.setType(ResVReg, |
| 105 | + LLT::scalar(GR->getScalarOrVectorBitWidth(ResType))); |
| 106 | + GR->assignSPIRVTypeToVReg(ResType, ResVReg, *GR->CurMF); |
| 107 | + } |
| 108 | + } |
| 109 | + } else if (mayBeInserted(Opcode) && I.getNumDefs() == 1 && |
| 110 | + I.getNumOperands() > 1 && I.getOperand(1).isReg()) { |
| 111 | + // Legalizer may have added a new instructions and introduced new |
| 112 | + // registers, we must decorate them as if they were introduced in a |
| 113 | + // non-automatic way |
| 114 | + Register ResVReg = I.getOperand(0).getReg(); |
| 115 | + SPIRVType *ResVType = GR->getSPIRVTypeForVReg(ResVReg); |
| 116 | + // Check if the register defined by the instruction is newly generated |
| 117 | + // or already processed |
| 118 | + if (!ResVType) { |
| 119 | + // Set type of the defined register |
| 120 | + ResVType = GR->getSPIRVTypeForVReg(I.getOperand(1).getReg()); |
| 121 | + // Check if we have type defined for operands of the new instruction |
| 122 | + if (!ResVType) |
| 123 | + continue; |
| 124 | + // Set type & class |
| 125 | + MRI.setRegClass(ResVReg, &SPIRV::IDRegClass); |
| 126 | + MRI.setType(ResVReg, |
| 127 | + LLT::scalar(GR->getScalarOrVectorBitWidth(ResVType))); |
| 128 | + GR->assignSPIRVTypeToVReg(ResVType, ResVReg, *GR->CurMF); |
| 129 | + } |
| 130 | + // If this is a simple operation that is to be reduced by TableGen |
| 131 | + // definition we must apply some of pre-legalizer rules here |
| 132 | + if (isTypeFoldingSupported(Opcode)) { |
| 133 | + // Check if the instruction newly generated or already processed |
| 134 | + MachineInstr *NextMI = I.getNextNode(); |
| 135 | + if (NextMI && isMetaInstrGET(NextMI->getOpcode())) |
| 136 | + continue; |
| 137 | + // Restore usual instructions pattern for the newly inserted |
| 138 | + // instruction |
| 139 | + MRI.setRegClass(ResVReg, MRI.getType(ResVReg).isVector() |
| 140 | + ? &SPIRV::IDRegClass |
| 141 | + : &SPIRV::ANYIDRegClass); |
| 142 | + MRI.setType(ResVReg, LLT::scalar(32)); |
| 143 | + insertAssignInstr(ResVReg, nullptr, ResVType, GR, MIB, MRI); |
| 144 | + processInstr(I, MIB, MRI, GR); |
| 145 | + } |
| 146 | + } |
| 147 | + } |
| 148 | + } |
| 149 | +} |
| 150 | + |
| 151 | +bool SPIRVPostLegalizer::runOnMachineFunction(MachineFunction &MF) { |
| 152 | + // Initialize the type registry. |
| 153 | + const SPIRVSubtarget &ST = MF.getSubtarget<SPIRVSubtarget>(); |
| 154 | + SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry(); |
| 155 | + GR->setCurrentFunc(MF); |
| 156 | + MachineIRBuilder MIB(MF); |
| 157 | + |
| 158 | + processNewInstrs(MF, GR, MIB); |
| 159 | + |
| 160 | + return true; |
| 161 | +} |
| 162 | + |
| 163 | +INITIALIZE_PASS(SPIRVPostLegalizer, DEBUG_TYPE, "SPIRV post legalizer", false, |
| 164 | + false) |
| 165 | + |
| 166 | +char SPIRVPostLegalizer::ID = 0; |
| 167 | + |
| 168 | +FunctionPass *llvm::createSPIRVPostLegalizerPass() { |
| 169 | + return new SPIRVPostLegalizer(); |
| 170 | +} |
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