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ElvinaYakubovaElvinaYakubova
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[AArch64] Add optional extensions enabled on Grace (llvm#127620)
Enable optional ISA extensions on Grace when mcpu=grace is used: sve2-sm4, sve2-aes, sve2-sha3. Grace is no longer an alias, but a separate CPU definition.
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‎clang/test/Driver/aarch64-mcpu.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@
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// COBALT-100: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2"
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// RUN: %clang --target=aarch64 -mcpu=grace -### -c %s 2>&1 | FileCheck -check-prefix=GRACE %s
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// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2"
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// GRACE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "grace"
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// ================== Check whether -mcpu and -mtune accept mixed-case values.
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// RUN: %clang --target=aarch64 -mcpu=Cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-CA53 %s

‎clang/test/Driver/print-enabled-extensions/aarch64-grace.c

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@@ -0,0 +1,62 @@
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// REQUIRES: aarch64-registered-target
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// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=grace | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: Extensions enabled for the given AArch64 target
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// CHECK-EMPTY:
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// CHECK-NEXT: Architecture Feature(s) Description
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// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support
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// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
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// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
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// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
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// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
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// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
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// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
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// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
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// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
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// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
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// CHECK-NEXT: FEAT_DotProd Enable dot product support
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// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
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// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
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// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
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// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
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// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
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// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
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// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
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// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
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// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
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// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
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// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
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// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
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// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
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// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
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// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
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// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
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// CHECK-NEXT: FEAT_RNG Enable Random Number generation instructions
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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support
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// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
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// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
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// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
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// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions
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// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
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// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions
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// CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1059,7 +1059,6 @@ def ProcessorFeatures {
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FeatureJS, FeatureLSE, FeaturePAuth, FeatureRAS, FeatureRCPC,
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FeatureCCIDX,
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FeatureRDM];
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list<SubtargetFeature> Oryon = [HasV8_6aOps, FeatureNEON, FeaturePerfMon,
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FeatureRandGen,
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FeaturePAuth, FeatureSM4, FeatureSHA2,
@@ -1068,6 +1067,7 @@ def ProcessorFeatures {
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FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8,
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FeatureSSBS, FeatureCCIDX,
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FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM];
1070+
list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVE2SHA3]);
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10721072
// ETE and TRBE are future architecture extensions. We temporarily enable them
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// by default for users targeting generic AArch64. The extensions do not
@@ -1151,6 +1151,8 @@ def : ProcessorModel<"cortex-x4", NeoverseV2Model, ProcessorFeatures.X4,
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[TuneX4]>;
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def : ProcessorModel<"cortex-x925", NeoverseV2Model, ProcessorFeatures.X925,
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[TuneX925]>;
1154+
def : ProcessorModel<"grace", NeoverseV2Model, ProcessorFeatures.Grace,
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[TuneNeoverseV2]>;
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def : ProcessorModel<"neoverse-e1", CortexA53Model,
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ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
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def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
@@ -1166,7 +1168,6 @@ def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
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ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
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def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
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ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
1169-
def : ProcessorAlias<"grace", "neoverse-v2">;
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def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
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ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
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def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,

‎llvm/test/CodeGen/AArch64/cpus.ll

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@@ -18,6 +18,7 @@
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a77 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a78 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-x1 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=grace 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-e1 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n1 2>&1 | FileCheck %s
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; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n2 2>&1 | FileCheck %s

‎llvm/unittests/TargetParser/TargetParserTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1167,6 +1167,7 @@ INSTANTIATE_TEST_SUITE_P(
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AArch64CPUTestParams("a64fx", "armv8.2-a"),
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AArch64CPUTestParams("fujitsu-monaka", "armv9.3-a"),
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AArch64CPUTestParams("carmel", "armv8.2-a"),
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AArch64CPUTestParams("grace", "armv9-a"),
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AArch64CPUTestParams("saphira", "armv8.4-a"),
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AArch64CPUTestParams("oryon-1", "armv8.6-a")),
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AArch64CPUTestParams::PrintToStringParamName);
@@ -1247,7 +1248,6 @@ TEST_P(AArch64CPUAliasTestFixture, testCPUAlias) {
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INSTANTIATE_TEST_SUITE_P(
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AArch64CPUAliasTests, AArch64CPUAliasTestFixture,
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::testing::Values(AArch64CPUAliasTestParams({"neoverse-n2", "cobalt-100"}),
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AArch64CPUAliasTestParams({"neoverse-v2", "grace"}),
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AArch64CPUAliasTestParams({"apple-a7", "cyclone",
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"apple-a8", "apple-a9"}),
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AArch64CPUAliasTestParams({"apple-a12", "apple-s4",

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