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lines changed Original file line number Diff line number Diff line change @@ -7,4 +7,7 @@ zephyr_library_sources(soc.c)
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zephyr_include_directories (. )
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- set (SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR} /linker.ld CACHE INTERNAL "" )
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+ # Add the image definition block if required
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+ zephyr_linker_sources (ROM_START rom_start.ld )
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+
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+ set (SOC_LINKER_SCRIPT ${ZEPHYR_BASE} /include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "" )
Original file line number Diff line number Diff line change @@ -7,7 +7,6 @@ config SOC_SERIES_RP2350
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select HAS_RPI_PICO
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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select SOC_RESET_HOOK
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- select XIP
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config SOC_RP2350A_M33
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select ARM
@@ -31,7 +30,7 @@ config SOC_RP2350B_M33
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config RP2_REQUIRES_IMAGE_DEFINITION_BLOCK
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bool
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- default y if FLASH_LOAD_OFFSET = 0x100
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+ default y
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# Currently the IDF only supports using the Cortex-M33 cores. Enforce
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# this at build configuration time.
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depends on SOC_SERIES_RP2350 && CPU_CORTEX_M33
Load Diff This file was deleted.
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+ /* rom_start.ld - additional data to append at the ROM start */
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+
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+ /*
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+ * Copyright (c) 2024 Andrew Featherstone
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+ *
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+ * SPDX-License-Identifier : Apache-2.0
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+ */
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+
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+ #if CONFIG_RP2_REQUIRES_IMAGE_DEFINITION_BLOCK
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+ LONG (0xffffded3 ) /* PICOBIN_BLOCK_MARKER_START */
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+ LONG (0x10210142 ) /* IMAGE_DEF Item */
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+ LONG (0x00000203 ) /* VECTOR_TABLE Item */
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+ LONG (ABSOLUTE(_vector_start )) /* - Address of the vector table in flash */
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+ LONG (0x000003ff ) /* Last Item in Block */
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+ LONG (0x00000000 ) /* End of block loop */
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+ LONG (0xab123579 ) /* PICOBIN_BLOCK_MARKER_END */
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+ #endif /* CONFIG_RP2_REQUIRES_IMAGE_DEFINITION_BLOCK */
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