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Commit 71cdced

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SitaraSitara
Sitara
authored and
Sitara
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Add stalling fixes
1 parent de32853 commit 71cdced

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2 files changed

+3
-3
lines changed

2 files changed

+3
-3
lines changed

PROC/PROCv2.vhd

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,7 @@ MEMstage: MEM port map(clk,mem_reset,mem_data_in_buffer,mem_address_in_buffer,me
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clk<=clock;
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id_reset<=reset;
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ex_reset<=reset;
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ex_reset<=reset AND NOT(enable_stall);
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if_reset<=reset;
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mem_reset<=reset;
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PROC/TEST2.tcl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ sim:/PROCv2/id_reset\
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sim:/PROCv2/if_reset\
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sim:/PROCv2/mem_reset
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10-
add wave -group "Hazard Detection" sim:/PROCv3/enable_stall
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add wave -group "Hazard Detection" sim:/PROCv2/enable_stall
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add wave -group "IF in buffers" sim:/PROCv2/if_pc_in_buffer\
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sim:/PROCv2/if_pc_sel_in_buffer\
@@ -93,7 +93,7 @@ add wave -position end sim:/procv2/EXstage/mux1/ctl
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;
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proc runsim {} {
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vsim PROCv2
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vsim PROCv2 -t ps
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AddWaves
9999
;#run 1 ns

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