core.thread: Add support for AArch64

Author: kinke

src/core/thread.d

@@ -3539,6 +3539,15 @@ private
             version = AsmExternal;
         }
     }
+    else version( AArch64 )
+    {
+        version( Posix )
+        {
+            version = AsmAArch64_Posix;
+            version = AsmExternal;
+            version = AlignFiberStackTo16Byte;
+        }
+    }
     else version( ARM )
     {
         version( Posix )
@@ -4870,6 +4879,29 @@ private:
             pstack -= ABOVE;
             *cast(size_t*)(pstack - SZ_RA) = cast(size_t)&fiber_entryPoint;
         }
+        else version( AsmAArch64_Posix )
+        {
+            // Like others, FP registers and return address (lr) are kept
+            // below the saved stack top (tstack) to hide from GC scanning.
+            // fiber_switchContext expects newp sp to look like this:
+            //   19: x19
+            //   ...
+            //    9: x29 (fp)  <-- newp tstack
+            //    8: x30 (lr)  [&fiber_entryPoint]
+            //    7: d8
+            //   ...
+            //    0: d15
+
+            version( StackGrowsDown ) {}
+            else
+                static assert(false, "Only full descending stacks supported on AArch64");
+
+            // Only need to set return address (lr).  Everything else is fine
+            // zero initialized.
+            pstack -= size_t.sizeof * 11;    // skip past x19-x29
+            push(cast(size_t) &fiber_entryPoint);
+            pstack += size_t.sizeof;         // adjust sp (newp) above lr
+        }
         else version( AsmARM_Posix )
         {
             /* We keep the FP registers and the return address below

src/core/threadasm.S

@@ -449,4 +449,59 @@ fiber_switchContext:
     // return by writing lr into pc
     mov pc, r1
     .fnend
+
+#elif defined(__aarch64__)
+/************************************************************************************
+ * AArch64 (arm64) ASM BITS
+ ************************************************************************************/
+/**
+ * preserve/restore AAPCS64 registers
+ *   x19-x28 5.1.1 64-bit callee saved
+ *   x29 fp, or possibly callee saved reg - depends on platform choice 5.2.3)
+ *   x30 lr
+ *   d8-d15  5.1.2 says callee only must save bottom 64-bits (the "d" regs)
+ *
+ * saved regs on stack will look like:
+ *   19: x19
+ *   18: x20
+ *   ...
+ *   10: x28
+ *    9: x29 (fp)  <-- oldp / *newp save stack top
+ *    8: x30 (lr)
+ *    7: d8
+ *   ...
+ *    0: d15       <-- sp
+ */
+        .text
+        .global CSYM(fiber_switchContext)
+        .p2align  2
+CSYM(fiber_switchContext):
+        stp     d15, d14, [sp, #-20*8]!
+        stp     d13, d12, [sp, #2*8]
+        stp     d11, d10, [sp, #4*8]
+        stp     d9, d8,   [sp, #6*8]
+        stp     x30, x29, [sp, #8*8] // lr, fp
+        stp     x28, x27, [sp, #10*8]
+        stp     x26, x25, [sp, #12*8]
+        stp     x24, x23, [sp, #14*8]
+        stp     x22, x21, [sp, #16*8]
+        stp     x20, x19, [sp, #18*8]
+
+        // oldp is set above saved lr (x30) to hide it and float regs
+        // from GC
+        add     x19, sp, #9*8
+        str     x19, [x0]       // *oldp tstack
+        sub     sp, x1, #9*8    // switch to newp sp
+
+        ldp     x20, x19, [sp, #18*8]
+        ldp     x22, x21, [sp, #16*8]
+        ldp     x24, x23, [sp, #14*8]
+        ldp     x26, x25, [sp, #12*8]
+        ldp     x28, x27, [sp, #10*8]
+        ldp     x30, x29, [sp, #8*8] // lr, fp
+        ldp     d9, d8,   [sp, #6*8]
+        ldp     d11, d10, [sp, #4*8]
+        ldp     d13, d12, [sp, #2*8]
+        ldp     d15, d14, [sp], #20*8
+        ret
 #endif