Winch: avoid emitting 32->64 extend on rmw ops on x64 (bytecodealliance#10037)

* avoid emitting 32->64 extend on rmw ops on x64

* review edit

Author: MarinPostma

tests/disas/winch/x64/atomic/rmw/i64_atomic_rmw32_subu.wat

@@ -12,7 +12,7 @@
 ;;       movq    0x10(%r11), %r11
 ;;       addq    $0x10, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x61
+;;       ja      0x5f
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x10, %rsp
 ;;       movq    %rdi, 8(%rsp)
@@ -21,16 +21,15 @@
 ;;       movl    $0, %ecx
 ;;       andl    $3, %ecx
 ;;       cmpl    $0, %ecx
-;;       jne     0x63
+;;       jne     0x61
 ;;   44: movl    $0, %ecx
 ;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       addq    %rcx, %rdx
 ;;       negl    %eax
 ;;       lock xaddl %eax, (%rdx)
-;;       movl    %eax, %eax
 ;;       addq    $0x10, %rsp
 ;;       popq    %rbp
 ;;       retq
+;;   5f: ud2
 ;;   61: ud2
-;;   63: ud2

winch/codegen/src/isa/x64/masm.rs

@@ -1413,8 +1413,12 @@ impl Masm for MacroAssembler {
         }
 
         if let Some(extend) = extend {
-            self.asm.movzx_rr(operand.to_reg(), operand, extend);
+            // We don't need to zero-extend from 32 to 64bits.
+            if !(extend.from_bits() == 32 && extend.to_bits() == 64) {
+                self.asm.movzx_rr(operand.to_reg(), operand, extend);
+            }
         }
+
         Ok(())
     }
 }