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Winch: Even tighter Extends (bytecodealliance#10066)
* tighter extends * Even thighter extends * rename src/dst_size to from/to_size
1 parent 4d75ebd commit 362568b

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7 files changed

+188
-194
lines changed

7 files changed

+188
-194
lines changed

‎winch/codegen/src/codegen/mod.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@ use crate::{
33
codegen::BlockSig,
44
isa::reg::{writable, Reg},
55
masm::{
6-
Imm, IntCmpKind, LoadKind, MacroAssembler, MemOpKind, OperandSize, RegImm, RmwOp, SPOffset,
7-
ShiftKind, TrapCode, UnsignedExtend, UNTRUSTED_FLAGS,
6+
Extend, Imm, IntCmpKind, LoadKind, MacroAssembler, MemOpKind, OperandSize, RegImm, RmwOp,
7+
SPOffset, ShiftKind, TrapCode, Zero, UNTRUSTED_FLAGS,
88
},
99
stack::TypedReg,
1010
};
@@ -1368,7 +1368,7 @@ where
13681368
arg: &MemArg,
13691369
op: RmwOp,
13701370
size: OperandSize,
1371-
extend: Option<UnsignedExtend>,
1371+
extend: Option<Extend<Zero>>,
13721372
) -> Result<()> {
13731373
// We need to pop-push the operand to compute the address before passing control over to
13741374
// masm, because some architectures may have specific requirements for the registers used

‎winch/codegen/src/isa/aarch64/asm.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
use super::{address::Address, regs};
33
use crate::aarch64::regs::zero;
44
use crate::masm::{
5-
DivKind, ExtendKind, FloatCmpKind, IntCmpKind, RemKind, RoundingMode, ShiftKind, SignedExtend,
6-
TruncKind,
5+
DivKind, Extend, ExtendKind, FloatCmpKind, IntCmpKind, RemKind, RoundingMode, ShiftKind,
6+
Signed, TruncKind,
77
};
88
use crate::CallingConvention;
99
use crate::{
@@ -444,12 +444,12 @@ impl Assembler {
444444
self.extend(
445445
divisor,
446446
writable!(divisor),
447-
ExtendKind::Signed(SignedExtend::I64Extend32S),
447+
ExtendKind::Signed(Extend::<Signed>::I64Extend32),
448448
);
449449
self.extend(
450450
dividend,
451451
writable!(dividend),
452-
ExtendKind::Signed(SignedExtend::I64Extend32S),
452+
ExtendKind::Signed(Extend::<Signed>::I64Extend32),
453453
);
454454
OperandSize::S64
455455
} else {
@@ -483,12 +483,12 @@ impl Assembler {
483483
self.extend(
484484
divisor,
485485
writable!(divisor),
486-
ExtendKind::Signed(SignedExtend::I64Extend32S),
486+
ExtendKind::Signed(Extend::<Signed>::I64Extend32),
487487
);
488488
self.extend(
489489
dividend,
490490
writable!(dividend),
491-
ExtendKind::Signed(SignedExtend::I64Extend32S),
491+
ExtendKind::Signed(Extend::<Signed>::I64Extend32),
492492
);
493493
OperandSize::S64
494494
} else {

‎winch/codegen/src/isa/aarch64/masm.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,10 @@ use crate::{
1212
CallingConvention,
1313
},
1414
masm::{
15-
CalleeKind, DivKind, ExtendKind, ExtractLaneKind, FloatCmpKind, Imm as I, IntCmpKind,
16-
LoadKind, MacroAssembler as Masm, MemOpKind, MulWideKind, OperandSize, RegImm, RemKind,
17-
RmwOp, RoundingMode, SPOffset, ShiftKind, SplatKind, StackSlot, TrapCode, TruncKind,
18-
UnsignedExtend,
15+
CalleeKind, DivKind, Extend, ExtendKind, ExtractLaneKind, FloatCmpKind, Imm as I,
16+
IntCmpKind, LoadKind, MacroAssembler as Masm, MemOpKind, MulWideKind, OperandSize, RegImm,
17+
RemKind, RmwOp, RoundingMode, SPOffset, ShiftKind, SplatKind, StackSlot, TrapCode,
18+
TruncKind, Zero,
1919
},
2020
stack::TypedReg,
2121
};
@@ -914,7 +914,7 @@ impl Masm for MacroAssembler {
914914
_size: OperandSize,
915915
_op: RmwOp,
916916
_flags: MemFlags,
917-
_extend: Option<UnsignedExtend>,
917+
_extend: Option<Extend<Zero>>,
918918
) -> Result<()> {
919919
Err(anyhow!(CodeGenError::unimplemented_masm_instruction()))
920920
}

‎winch/codegen/src/isa/x64/asm.rs

Lines changed: 19 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33
use crate::{
44
isa::{reg::Reg, CallingConvention},
55
masm::{
6-
DivKind, ExtendKind, IntCmpKind, MulWideKind, OperandSize, RemKind, RoundingMode,
7-
ShiftKind, SignedExtend, UnsignedExtend, VectorExtendKind,
6+
DivKind, Extend, ExtendKind, ExtendType, IntCmpKind, MulWideKind, OperandSize, RemKind,
7+
RoundingMode, ShiftKind, Signed, VectorExtendKind, Zero,
88
},
99
reg::writable,
1010
x64::regs::scratch,
@@ -144,37 +144,24 @@ impl From<ShiftKind> for CraneliftShiftKind {
144144
}
145145
}
146146

147-
impl From<ExtendKind> for ExtMode {
148-
fn from(value: ExtendKind) -> Self {
147+
impl<T: ExtendType> From<Extend<T>> for ExtMode {
148+
fn from(value: Extend<T>) -> Self {
149149
match value {
150-
ExtendKind::Signed(s) => match s {
151-
SignedExtend::I32Extend8S => ExtMode::BL,
152-
SignedExtend::I32Extend16S => ExtMode::WL,
153-
SignedExtend::I64Extend8S => ExtMode::BQ,
154-
SignedExtend::I64Extend16S => ExtMode::WQ,
155-
SignedExtend::I64Extend32S => ExtMode::LQ,
156-
},
157-
ExtendKind::Unsigned(u) => match u {
158-
UnsignedExtend::I32Extend8U => ExtMode::BL,
159-
UnsignedExtend::I32Extend16U => ExtMode::WL,
160-
UnsignedExtend::I64Extend8U => ExtMode::BQ,
161-
UnsignedExtend::I64Extend16U => ExtMode::WQ,
162-
UnsignedExtend::I64Extend32U => ExtMode::LQ,
163-
},
150+
Extend::I32Extend8 => ExtMode::BL,
151+
Extend::I32Extend16 => ExtMode::WL,
152+
Extend::I64Extend8 => ExtMode::BQ,
153+
Extend::I64Extend16 => ExtMode::WQ,
154+
Extend::I64Extend32 => ExtMode::LQ,
155+
Extend::__Kind(_) => unreachable!(),
164156
}
165157
}
166158
}
167159

168-
impl From<OperandSize> for Option<ExtMode> {
169-
// Helper for cases in which it's known that the widening must be
170-
// to quadword.
171-
fn from(value: OperandSize) -> Self {
172-
use OperandSize::*;
160+
impl From<ExtendKind> for ExtMode {
161+
fn from(value: ExtendKind) -> Self {
173162
match value {
174-
S128 | S64 => None,
175-
S8 => Some(ExtMode::BQ),
176-
S16 => Some(ExtMode::WQ),
177-
S32 => Some(ExtMode::LQ),
163+
ExtendKind::Signed(s) => s.into(),
164+
ExtendKind::Unsigned(u) => u.into(),
178165
}
179166
}
180167
}
@@ -350,7 +337,7 @@ impl Assembler {
350337
&mut self,
351338
addr: &Address,
352339
dst: WritableReg,
353-
ext: Option<ExtMode>,
340+
ext: Option<Extend<Zero>>,
354341
memflags: MemFlags,
355342
) {
356343
let src = Self::to_synthetic_amode(
@@ -364,7 +351,7 @@ impl Assembler {
364351
if let Some(ext) = ext {
365352
let reg_mem = RegMem::mem(src);
366353
self.emit(Inst::MovzxRmR {
367-
ext_mode: ext,
354+
ext_mode: ext.into(),
368355
src: GprMem::unwrap_new(reg_mem),
369356
dst: dst.map(Into::into),
370357
});
@@ -381,7 +368,7 @@ impl Assembler {
381368
&mut self,
382369
addr: &Address,
383370
dst: WritableReg,
384-
ext: impl Into<ExtMode>,
371+
ext: Extend<Signed>,
385372
memflags: MemFlags,
386373
) {
387374
let src = Self::to_synthetic_amode(
@@ -401,7 +388,7 @@ impl Assembler {
401388
}
402389

403390
/// Register-to-register move with zero extension.
404-
pub fn movzx_rr(&mut self, src: Reg, dst: WritableReg, kind: ExtendKind) {
391+
pub fn movzx_rr(&mut self, src: Reg, dst: WritableReg, kind: Extend<Zero>) {
405392
self.emit(Inst::MovzxRmR {
406393
ext_mode: kind.into(),
407394
src: src.into(),
@@ -410,7 +397,7 @@ impl Assembler {
410397
}
411398

412399
/// Register-to-register move with sign extension.
413-
pub fn movsx_rr(&mut self, src: Reg, dst: WritableReg, kind: ExtendKind) {
400+
pub fn movsx_rr(&mut self, src: Reg, dst: WritableReg, kind: Extend<Signed>) {
414401
self.emit(Inst::MovsxRmR {
415402
ext_mode: kind.into(),
416403
src: src.into(),

‎winch/codegen/src/isa/x64/masm.rs

Lines changed: 28 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -7,10 +7,9 @@ use super::{
77
use anyhow::{anyhow, bail, Result};
88

99
use crate::masm::{
10-
DivKind, ExtendKind, ExtractLaneKind, FloatCmpKind, Imm as I, IntCmpKind, LoadKind,
10+
DivKind, Extend, ExtendKind, ExtractLaneKind, FloatCmpKind, Imm as I, IntCmpKind, LoadKind,
1111
MacroAssembler as Masm, MemOpKind, MulWideKind, OperandSize, RegImm, RemKind, RmwOp,
12-
RoundingMode, ShiftKind, SplatKind, TrapCode, TruncKind, UnsignedExtend, TRUSTED_FLAGS,
13-
UNTRUSTED_FLAGS,
12+
RoundingMode, ShiftKind, SplatKind, TrapCode, TruncKind, Zero, TRUSTED_FLAGS, UNTRUSTED_FLAGS,
1413
};
1514
use crate::{
1615
abi::{self, align_to, calculate_frame_adjustment, LocalSlot},
@@ -34,7 +33,7 @@ use cranelift_codegen::{
3433
isa::{
3534
unwind::UnwindInst,
3635
x64::{
37-
args::{ExtMode, FenceKind, CC},
36+
args::{FenceKind, CC},
3837
settings as x64_settings, AtomicRmwSeqOp,
3938
},
4039
},
@@ -246,7 +245,12 @@ impl Masm for MacroAssembler {
246245
let _ = match (dst.to_reg().class(), size) {
247246
(RegClass::Int, OperandSize::S32) => {
248247
let addr = self.address_from_sp(current_sp)?;
249-
self.asm.movzx_mr(&addr, dst, size.into(), TRUSTED_FLAGS);
248+
self.asm.movzx_mr(
249+
&addr,
250+
dst,
251+
size.extend_to::<Zero>(OperandSize::S64),
252+
TRUSTED_FLAGS,
253+
);
250254
self.free_stack(size.bytes())?;
251255
}
252256
(RegClass::Int, OperandSize::S64) => {
@@ -313,10 +317,13 @@ impl Masm for MacroAssembler {
313317
bail!(CodeGenError::unexpected_operand_size());
314318
}
315319

316-
if ext.signed() {
317-
self.asm.movsx_mr(&src, dst, ext, UNTRUSTED_FLAGS);
318-
} else {
319-
self.load_impl::<Self>(src, dst, size, UNTRUSTED_FLAGS)?
320+
match ext {
321+
ExtendKind::Signed(ext) => {
322+
self.asm.movsx_mr(&src, dst, ext, UNTRUSTED_FLAGS);
323+
}
324+
ExtendKind::Unsigned(_) => {
325+
self.load_impl::<Self>(src, dst, size, UNTRUSTED_FLAGS)?
326+
}
320327
}
321328
}
322329
LoadKind::Operand(_) => {
@@ -1040,11 +1047,15 @@ impl Masm for MacroAssembler {
10401047
}
10411048

10421049
fn extend(&mut self, dst: WritableReg, src: Reg, kind: ExtendKind) -> Result<()> {
1043-
if !kind.signed() {
1044-
self.asm.movzx_rr(src, dst, kind);
1045-
} else {
1046-
self.asm.movsx_rr(src, dst, kind);
1050+
match kind {
1051+
ExtendKind::Signed(ext) => {
1052+
self.asm.movsx_rr(src, dst, ext);
1053+
}
1054+
ExtendKind::Unsigned(ext) => {
1055+
self.asm.movzx_rr(src, dst, ext);
1056+
}
10471057
}
1058+
10481059
Ok(())
10491060
}
10501061

@@ -1126,7 +1137,7 @@ impl Masm for MacroAssembler {
11261137
self.extend(
11271138
writable!(src),
11281139
src,
1129-
ExtendKind::Unsigned(UnsignedExtend::I64Extend32U),
1140+
ExtendKind::Unsigned(Extend::I64Extend32),
11301141
)?;
11311142
}
11321143

@@ -1422,7 +1433,7 @@ impl Masm for MacroAssembler {
14221433
size: OperandSize,
14231434
op: RmwOp,
14241435
flags: MemFlags,
1425-
extend: Option<UnsignedExtend>,
1436+
extend: Option<Extend<Zero>>,
14261437
) -> Result<()> {
14271438
let res = match op {
14281439
RmwOp::Add => {
@@ -1598,16 +1609,8 @@ impl MacroAssembler {
15981609
M: Masm,
15991610
{
16001611
if dst.to_reg().is_int() {
1601-
let access_bits = size.num_bits() as u16;
1602-
1603-
let ext_mode = match access_bits {
1604-
8 => Some(ExtMode::BQ),
1605-
16 => Some(ExtMode::WQ),
1606-
32 => Some(ExtMode::LQ),
1607-
_ => None,
1608-
};
1609-
1610-
self.asm.movzx_mr(&src, dst, ext_mode, flags);
1612+
let ext = size.extend_to::<Zero>(OperandSize::S64);
1613+
self.asm.movzx_mr(&src, dst, ext, flags);
16111614
} else {
16121615
self.asm.xmm_mov_mr(&src, dst, size, flags);
16131616
}

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