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1 parent e4a41f3 commit a91e014Copy full SHA for a91e014
cores/arduino/wiring.c
@@ -138,8 +138,12 @@ void init( void )
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DAC->CTRLA.bit.SWRST = 1;
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while ( DAC->SYNCBUSY.bit.SWRST == 1 ); // Wait for synchronization of registers between the clock domains
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- DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU; // TODO: make this work with VDDANA
+ DAC->CTRLB.reg = DAC_CTRLB_REFSEL_VREFPU; // TODO: fix this once silicon bug is fixed
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+ //set refresh rates
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+ DAC->DACCTRL[0].bit.REFRESH = 2;
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+ DAC->DACCTRL[1].bit.REFRESH = 2;
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+
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#else
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while(GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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