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Clarifications on non-indirect-bus reference nodes in address-map #168

@mbolivar-nordic

Description

@mbolivar-nordic

I could use some general clarification on what happens if a device
node is directly mapped into an address-map property, but it's the
child of one or more nodes which are not visible to the
corresponding CPU cluster.

Abstractly, the idea that "the node is visible but its parents aren't"
doesn't quite make sense to me from the perspective of how to generate
an equivalent standard devicetree.

For example:

/ {
	cpu0: cpu0-cluster {
		compatible = "cpus,cluster";
		#address-cells = <1>;
		#size-cells = <0>;
		#ranges-address-cells = <1>;
		#ranges-size-cells = <1>;

		/* Non-secure address map. */
		address-map = <0 &peripheral 0 0x1000>;

		/* ... */
	};

	bus {
		compatible = "indirect-bus";
		intermediate-node@... {
			peripheral: peripheral@... {
				reg = <... 0x1000>;
			};
		};
	}
};

It's not clear to me how to generate a standard devicetree for this
that both preserves the structure of the original system devicetree
and respects visibility within an address map.

Can we introduce some sensible restrictions on non-bus nodes in
address-map properties to avoid ambiguity here?

For example, one rule which would clear it up for me would be "such
nodes must be children of the root node". Then there's no problem with
intermediate nodes, and address translation through the root node's
#address-cells and #size-cells properties seems trivial, since the
peripheral is already directly underneath the root.

I was thinking perhaps we need some sort of rule along these lines:

  • you have to have explicit address translation via ranges
    properties as needed all the way from the root to the node you are
    mapping in via address-map

  • all the nodes along the path from root to the peripheral
    have to be mapped into the address-map too

But that seems to break other simple cases, like mapping in a SPI or
I2C slave:

/ {
	bus {
		compatible = "indirect-bus";
		spi@deadbeef {
			cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
			sensor@0 { /* ... */ };
		};
	}
};

Here it seems clear that we want sensor@0 mapped into the CPU
cluster if we map in bus, so there must be some sort of transitive
inclusion of child nodes when you map in parent nodes, at least for
indirect-bus nodes.

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