set-associative cache ways

[cf-natali]

perf-book/chapters/3-CPU-Microarchitecture/3-5 Memory Hierarchy.md

Line 28 in 696c52a

An intermediate option between the direct mapping and fully associative mapping is a set-associative mapping. In such a cache, the blocks are organized as sets, typically each set containing 2,4 or 8 blocks. A given address is first mapped to a set. Within a set, the address can be placed anywhere, among the blocks in that set. A cache with m blocks per set is described as an m-way set-associative cache. The formulas for a set-associative cache are:

An intermediate option between the direct mapping and fully associative mapping is a set-associative mapping. In such a cache, the blocks are organized as sets, typically each set containing 2,4 or 8 blocks.

On Zen 4, the L3 is 16-way, might be worth updating?

[dendibakh]

Yes, feel free to submit a PR.

[cf-natali]

#25