Add unratified Smclic, Ssclic, Smclicshv extensions

Spec: https://github.com/riscv/riscv-fast-interrupt
Tests: riscv-non-isa/riscv-arch-test#436

Author: dansmathers

ocaml_emulator/platform.ml

@@ -102,6 +102,9 @@ let dram_size ()  = arch_bits_of_int64 !P.dram_size_ref
 let clint_base () = arch_bits_of_int64 P.clint_base
 let clint_size () = arch_bits_of_int64 P.clint_size
 
+let clic_base () = arch_bits_of_int64 P.clic_base
+let clic_size () = arch_bits_of_int64 P.clic_size
+
 let insns_per_tick () = Big_int.of_int P.insns_per_tick
 
 let htif_tohost () =
@@ -165,6 +168,7 @@ let init arch elf_file =
 
   print_platform (Printf.sprintf "\nRegistered htif_tohost at 0x%Lx.\n" (Big_int.to_int64 (Elf.elf_tohost ())));
   print_platform (Printf.sprintf "Registered clint at 0x%Lx (size 0x%Lx).\n%!" P.clint_base P.clint_size);
+  print_platform (Printf.sprintf "Registered clic at 0x%Lx (size 0x%Lx).\n%!" P.clic_base P.clic_size);
 
   let start_pc = Elf.Big_int.to_int64 (Elf.elf_entry ()) in
   let rom = make_rom arch start_pc in

ocaml_emulator/platform_impl.ml

@@ -53,6 +53,8 @@ let reset_vec_int arch start_pc = [
 let dram_base  = 0x80000000L;;  (* Spike::DRAM_BASE *)
 let clint_base = 0x02000000L;;  (* Spike::CLINT_BASE *)
 let clint_size = 0x000c0000L;;  (* Spike::CLINT_SIZE *)
+let clic_base = 0x04000000L;;  (* Spike::MCLIC_BASE *)
+let clic_size = 0x000c0000L;;  (* Spike::CLIC_SIZE *)
 let rom_base   = 0x00001000L;;  (* Spike::DEFAULT_RSTVEC *)
 
 let dram_size_ref = ref (Int64.(shift_left 64L 20))
@@ -108,6 +110,12 @@ let spike_dts isa_spec mmu_spec cpu_hz insns_per_rtc_tick mems =
   ^ "      reg = <0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical clint_base 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand clint_base 0xffffffffL)
   ^             " 0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical clint_size 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand clint_size 0xffffffffL) ^ ">;\n"
   ^ "    };\n"
+  ^ "    clic@" ^ Printf.sprintf "%Lx" clic_base ^ " {\n"
+  ^ "      compatible = \"riscv,clic0\";\n"
+  ^ "      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;\n"
+  ^ "      reg = <0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical clic_base 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand clic_base 0xffffffffL)
+  ^             " 0x" ^ Printf.sprintf "%Lx" Int64.(shift_right_logical clic_size 32) ^ " 0x" ^ Printf.sprintf "%Lx" Int64.(logand clic_size 0xffffffffL) ^ ">;\n"
+  ^ "    };\n"
   ^ "  };\n"
   ^ "  htif {\n"
   ^ "    compatible = \"ucb,htif0\";\n"