Add unratified Smclic, Ssclic, Smclicshv extensions

Spec: https://github.com/riscv/riscv-fast-interrupt
Tests: riscv-non-isa/riscv-arch-test#436

Author: dansmathers

c_emulator/riscv_platform.c

@@ -113,6 +113,16 @@ mach_bits plat_clint_size(unit u)
   return rv_clint_size;
 }
 
+mach_bits plat_clic_base(unit u)
+{
+  return rv_clic_base;
+}
+
+mach_bits plat_clic_size(unit u)
+{
+  return rv_clic_size;
+}
+
 unit load_reservation(mach_bits addr)
 {
   reservation = addr;

c_emulator/riscv_platform.h

@@ -29,6 +29,9 @@ mach_bits plat_get_16_random_bits();
 mach_bits plat_clint_base(unit);
 mach_bits plat_clint_size(unit);
 
+mach_bits plat_clic_base(unit);
+mach_bits plat_clic_size(unit);
+
 bool speculate_conditional(unit);
 unit load_reservation(mach_bits);
 bool match_reservation(mach_bits);

c_emulator/riscv_platform_impl.c

@@ -42,6 +42,9 @@ uint64_t rv_16_random_bits(void)
 uint64_t rv_clint_base = UINT64_C(0x2000000);
 uint64_t rv_clint_size = UINT64_C(0xc0000);
 
+uint64_t rv_clic_base = UINT64_C(0x4000000);
+uint64_t rv_clic_size = UINT64_C(0xc0000);
+
 uint64_t rv_htif_tohost = UINT64_C(0x80001000);
 uint64_t rv_insns_per_tick = UINT64_C(100);
 

c_emulator/riscv_platform_impl.h

@@ -34,6 +34,9 @@ extern uint64_t rv_16_random_bits(void);
 extern uint64_t rv_clint_base;
 extern uint64_t rv_clint_size;
 
+extern uint64_t rv_clic_base;
+extern uint64_t rv_clic_size;
+
 extern uint64_t rv_htif_tohost;
 extern uint64_t rv_insns_per_tick;
 

c_emulator/riscv_sim.c

@@ -616,6 +616,8 @@ void init_sail(uint64_t elf_entry)
     rv_rom_size = UINT64_C(0);
     rv_clint_base = UINT64_C(0);
     rv_clint_size = UINT64_C(0);
+    rv_clic_base = UINT64_C(0);
+    rv_clic_size = UINT64_C(0);
     rv_htif_tohost = UINT64_C(0);
     zPC = elf_entry;
   } else