Where to send corefreq-cli -s output?

[morten71]

On the CPU support page in the wiki, it says to add corefreq output. But I have no idea where to send my AMD 9950X3D info, so I'm going to try adding it here. Sorry if I've misunderstood something :-)

corefreq-cli-s.txt

[cyring]

Sorry, it's not that clear.
You were supposed to create your own GitHub Gist page where you show CLI outputs and various screenshots or shorts showing CoreFreq driving your processor.
Next you provide me the Gist link which I add to the wiki CPU support.

Rather than an issue, you can keep provide or exchange on things (ie Gist link) through Discussions

[morten71]

Ok thanks! Something like this maybe?

https://gist.github.com/morten71/0aad8fdb9c361a2d0428f9666fc0fb58

[cyring]

Nice. Do you mind to add:

• Topology corefreq-cli -m
• SMBIOS corefreq-cli -B
• Sensors corefreq-cli -C 1
  • when system idle
  • when system stressed

---

DIMM size has a bug, due to a wrong geometry decoding with new DRAM

[morten71]

Yeah I did notice the DIMM sizes were half of what they should be, but I had seen you write about that bug somewhere else, so I ignored it :-)

I have tried adding the things you mentioned... Happy to change it, if you need something else.

[cyring]

Looks great. Added to CPU list.

---

• Is it because the extended cache is stacked on half of the chip that we decode such L3 size per cluster or b/c Hybrid Cores or CoreFreq bug ?

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID CCD CCX ID/ID L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0   0  0   0  0      32  8        48 12      1024 16 i  196608 16w 
...
008:  0   16   1  2   8  0      32  8        48 12      1024 16 i   65536 16w 

• System idle, the 1.4250 Vcore can't be greater than voltage 1.3563 when stressed.
  That bug is due because voltage formula has been designed in only one User case.

[morten71]

• Is it because the extended cache is stacked on half of the chip that we decode such L3 size per cluster or b/c Hybrid Cores or CoreFreq bug ?

Yeah the 9950X3D has the 3D cache on only one of the chiplets, so there are 8 cores that can go to a slightly higher clock frequency, but they only have the small L3 cache, and then the other 8 cores have the big L3 cache, but can't go to quite the same max clock frequency. Cpus 0-7 and 16-23 are the extended cache cores. and cpus 8-15 and 24-31 have the smaller cache, but higher max clock... Or at least that is the simplified way I understand it :-)

I did wonder about the lower voltage in the stressed case, but I understand so little about the inner workings of CPUs, so I assumed there was something I just don't understand 😅

[cyring]

Yeah the 9950X3D has the 3D cache on only one of the chiplets, so there are 8 cores that can go to a slightly higher clock frequency

Thank you for this explaination. It's an uncommon architecture I would like to study.
Is stressing with Tools > Conics rather Atomic reveal the different cluster frequencies: can you please add such screenshot ?
Conics involves FPU and Math extensions.

[morten71]

ah I didn't see your reply here before... I will test that now.

[morten71]

This is how it looks with Conics (Ellipsoid) running:

[morten71]

I'll add these screenshots to the gist, to keep them in one place

[cyring]

The associated voltage VID of 228 and 217 are so closed values that I still don't understand what kind of math formula AMD has designed in this architecture ?

Within other architectures, idle and stressed cases are VID from the numerical range boundaries.

[cyring]

Very instructive screenshots.
Thank you.

If you believe frequencies should be greater on the lowest L3 cache size, perhaps CPPC and ACPI are messing governing P-states.

With my 3950X, I'm blacklisting the amd_pstate and acpi-idle from the kernel boot command line to have deterministic Target Ratios.
CoreFreq as the Clock Source, CPU Freq and CPU Idle driver
Once CoreFreq in control (CPU-Freq and CPU-Idle) I'm reaching the expecting specs frequencies with the addition of better benchmarks and still the benefits of lower sensors.

[cyring]

Conics trigger almost 200W

Conics > Two Planes is the most stressful function; Processor may consume more energy.

[morten71]

Very instructive screenshots. Thank you.

If you believe frequencies should be greater on the lowest L3 cache size, perhaps CPPC and ACPI are messing governing P-states.

With my 3950X, I'm blacklisting the amd_pstate and acpi-idle from the kernel boot command line to have deterministic Target Ratios. CoreFreq as the Clock Source, CPU Freq and CPU Idle driver Once CoreFreq in control (CPU-Freq and CPU-Idle) I'm reaching the expecting specs frequencies with the addition of better benchmarks and still the benefits of lower sensors.

Thank you! I will definitely try that out, and see what happens :-)

[morten71]

Conics trigger almost 200W

Conics > Two Planes is the most stressful function; Processor may consume more energy.

I got this with Two Planes, so still around 200W. But I'm guessing the power consumption is getting limited, when it gets to those levels? It's rated at 170W TDP, so the fact that it even gets to 200W is slightly surprising to me already. It's not good for my electricity bill definitely 😅

(Until very recently I had an Intel i9-9900K, which had a TDP of 95W, so this is quite a big jump for me)

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000 4884.09   175  1.0938   81  000000000000593662    9.058563232   9.058563232
001 4884.10   175  1.0938   81  000000000000607454    9.269012451   9.269012451
002 4883.31   175  1.0938   81  000000000000593827    9.061080933   9.061080933
003 4884.04   175  1.0938   81  000000000000606719    9.257797241   9.257797241
004 4884.04   175  1.0938   81  000000000000581851    8.878341675   8.878341675
005 4883.31   175  1.0938   81  000000000000622955    9.505538940   9.505538940
006 4883.31   175  1.0938   81  000000000000611159    9.325546265   9.325546265
007 4884.04   175  1.0938   81  000000000000622868    9.504211426   9.504211426
008 4849.73   175  1.0938   78  000000000000597119    9.111312866   9.111312866
009 4849.73   175  1.0938   78  000000000000602319    9.190658569   9.190658569
010 4849.68   175  1.0938   78  000000000000615117    9.385940552   9.385940552
011 4849.68   175  1.0938   78  000000000000609972    9.307434082   9.307434082
012 4849.69   175  1.0938   78  000000000000605538    9.239776611   9.239776611
013 4849.73   175  1.0938   78  000000000000611578    9.331939697   9.331939697
014 4849.73   175  1.0938   78  000000000000597265    9.113540649   9.113540649
015 4849.73   175  1.0938   78  000000000000598805    9.137039185   9.137039185
016 4884.04   175  1.0938   81  000000000000000000    0.000000000   0.000000000
017 4884.04   175  1.0938   81  000000000000000000    0.000000000   0.000000000
018 4884.09   175  1.0938   81  000000000000000000    0.000000000   0.000000000
019 4884.04   175  1.0938   81  000000000000000000    0.000000000   0.000000000
020 4883.27   175  1.0938   81  000000000000000000    0.000000000   0.000000000
021 4883.99   175  1.0938   81  000000000000000000    0.000000000   0.000000000
022 4884.04   175  1.0938   81  000000000000000000    0.000000000   0.000000000
023 4884.09   175  1.0938   81  000000000000000000    0.000000000   0.000000000
024 4849.73   175  1.0938   78  000000000000000000    0.000000000   0.000000000
025 4849.73   175  1.0938   78  000000000000000000    0.000000000   0.000000000
026 4848.28   175  1.0938   78  000000000000000000    0.000000000   0.000000000
027 4849.73   175  1.0938   78  000000000000000000    0.000000000   0.000000000
028 4849.73   175  1.0938   78  000000000000000000    0.000000000   0.000000000
029 4849.73   175  1.0938   78  000000000000000000    0.000000000   0.000000000
030 4847.50   175  1.0938   78  000000000000000000    0.000000000   0.000000000
031 4849.00   175  1.0938   78  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J): 199.993392944 147.677734375   0.000000000   0.000000000   0.000000000
Power(W) : 199.993392944 147.677734375   0.000000000   0.000000000   0.000000000

[cyring]

TDP of 170W, I can't really tell if it limits the sum of all Cores 147W or the Package Processor, including SOC, SLC LLC, and other Uncore

[cyring]

Forget looking at the CoreFreq VID, I believe the register specifications are out of date. Starting Zen4/Zen5 something had changed

REGISTERS

CoreFreq/x86_64/amd_reg.h

Line 565 in 2171321

unsigned long long /* MSR 0xC001_0293 Hardware P-state Status */

CoreFreq/x86_64/amd_reg.h

Line 548 in 2171321

unsigned long long /* MSR 0xC001_006[4...B] P-state [7:0] */

You can dig into the P-state registers using the MSR-Tools

## Boosted HW_PSTATE_STATUS
rdmsr -aX 0xC0010293

## PSTATEDEF - Family_1Ah
### P0 P-State
rdmsr -aX 0xC0010064
### P1 P-State
rdmsr -aX 0xC0010065

FREQUENCY

The Frequency CpuFid field used to compute the Coefficient of Frequency has changed since Zen5 generation.

Zen5 is the case of ExtFamily with value 0xB

CoreFreq/x86_64/corefreqk.c

Line 8114 in 2171321

static COF_ST AMD_Zen_CoreCOF(PSTATEDEF PStateDef)

---

VOLTAGE

• The original Zen1/Zen2, TR, EPYC

$$Vcore = 1.550 - (0.00625 * VID)$$

CoreFreq/x86_64/coretypes.h

Line 786 in 2171321

#define COMPUTE_VOLTAGE_AMD_17h(Vcore, VID) \

• Since Rembrandt, I have found this simplified formula to work

$$Vcore = 0.00625 * VID$$

CoreFreq/x86_64/coretypes.h

Line 789 in 2171321

#define COMPUTE_VOLTAGE_AMD_RMB(Vcore, VID) \

• With Raphael, we made some attempts to approximate Voltage based on VCO datasheet

$$Vcore = 2.09 - ((0.005 * (VID)) + 0.245)$$

CoreFreq/x86_64/coretypes.h

Line 792 in 2171321

#define COMPUTE_VOLTAGE_AMD_VCO(Vcore, VID) \

• Strangely with an EPYC 9654 Genoa, P-State VID can still be used with the simplified formula

$$Vcore = 0.00625 * 113 = 0.7063$$

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000   13.40   113  0.7063   43  000000000000000277    0.004226685   0.004226685
001    0.46   113  0.7063   43  000000000000000074    0.001129150   0.001129150
002    0.47   113  0.7063   43  000000000000000115    0.001754761   0.001754761
003    0.69   113  0.7063   43  000000000000000147    0.002243042   0.002243042
...
383    0.49   113  0.7063   43  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):  50.342239380   0.339157104  88.496002197   0.000000000   0.000000000
Power(W) :  50.342239380   0.339157104  88.496002197   0.000000000   0.000000000

---

ISSUE

But with Ryzen4/Ryzen5, I have no clue how to compute voltage with CpuVid and perhaps CpuVid8

[cyring]

Hello,

In this screenshot I can read a Voltage Core of 1.36 V which appears coherent with the load applied on the 9950X3D

All subsequent screenshots or outputs don't show a voltage going that high.

Can you tell if some BIOS voltage tweaks or performance profiles which involve voltage have been applied between the two test periods ?

If true could you determine which BIOS features are altering voltage reading compared to a nominal state ?

Thank you.