From 2055b3179b884007b5416872398089697f19b86b Mon Sep 17 00:00:00 2001 From: Craig Thomas Date: Tue, 10 Sep 2024 10:48:50 -0400 Subject: [PATCH] Fix right shift bit one bug. --- chip8/cpu.py | 2 +- test/test_chip8cpu.py | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/chip8/cpu.py b/chip8/cpu.py index da01272..8de9477 100644 --- a/chip8/cpu.py +++ b/chip8/cpu.py @@ -699,7 +699,7 @@ def right_shift_reg(self): self.v[0xF] = bit_one self.last_op = f"SHR V{x:01X}" else: - bit_one = self.v[x] & 0x1 + bit_one = self.v[y] & 0x1 self.v[x] = self.v[y] >> 1 self.v[0xF] = bit_one self.last_op = f"SHR V{x:01X}, V{y:01X}" diff --git a/test/test_chip8cpu.py b/test/test_chip8cpu.py index 8d42811..18296f2 100644 --- a/test/test_chip8cpu.py +++ b/test/test_chip8cpu.py @@ -399,6 +399,15 @@ def test_right_shift_reg(self): self.assertEqual(self.cpu.v[x], shifted_val) self.assertEqual(self.cpu.v[0xF], bit_zero) + def test_right_shift_reg_y_bug(self): + self.cpu.shift_quirks = False + self.cpu.operand = 0x0120 + self.cpu.v[1] = 0 + self.cpu.v[2] = 1 + self.cpu.right_shift_reg() + self.assertEqual(0, self.cpu.v[1]) + self.assertEqual(1, self.cpu.v[0xF]) + def test_subtract_reg_from_reg1(self): for x in range(0xF): for y in range(0xF):