[Backend] AMD Ryzen NPU Optimization

[chhzh123]

• https://riallto.ai/notebooks/3_2_Ryzenai_capabilities.html
• https://github.com/Xilinx/mlir-aie/tree/main/programming_guide
• https://github.com/Xilinx/mlir-aie/tree/main/programming_examples/basic

[chrisfxu]

single_core and whole_array benchmark results

[tmao8]

whole_array benchmark with 64x64x64 tiles results

[chhzh123]

@chrisfxu @tmao8 Your profiling results seem to differ a lot (>20%). Can you guys check what's going wrong? When doing profiling, please make sure

1. Conduct experiments for at least 1,000 iterations and take the average. If for large matrix sizes, it takes too long, then do 100 iterations.
2. Remove the results from the first 10 iterations (warm-up).
3. Control the variables: When changing the matrix sizes, fix the tile sizes; When changing tile sizes, fix matrix sizes. In the end, we want to figure out for each matrix shape, what the best configuration of tile sizes is.

[chrisfxu]

4/9:

Implemented tensor parallelism example with dataflow interface. Design working on simulator backend but not AIE.