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[SYCL][Doc] Use correct product name in extensions (intel#12053)
The correct name is "Intel(R) Data Center GPU Max Series".
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sycl/doc/extensions/supported/sycl_ext_intel_cslice.asciidoc

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== Notice
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[%hardbreaks]
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Copyright (C) 2022-2022 Intel Corporation. All rights reserved.
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Copyright (C) 2022-2023 Intel Corporation. All rights reserved.
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Khronos(R) is a registered trademark and SYCL(TM) and SPIR(TM) are trademarks
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of The Khronos Group Inc. OpenCL(TM) is a trademark of Apple Inc. used by
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`info::partition_property::ext_intel_partition_by_cslice`.
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The only Intel GPU devices that currently support this type of partitioning
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are the Data Center GPU Max series (aka PVC), and this support is only
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are the Intel(R) Data Center GPU Max Series (aka PVC), and this support is only
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available when the device driver is configured in {multi-CCS}[multi-CCS] mode.
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See that documentation for instructions on how to enable this mode and for
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other important information. Currently, it is only possible to partition a
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It is important to understand that the device driver virtualizes work
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submission to the cslice sub-devices. (More specifically, the device driver
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virtualizes work submission to different CCS-es, and this means that on Data
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Center GPU Max series devices the work submission to a cslice is virtualized.)
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This virtualization happens only between processes, and not within a single
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process. For example, consider a single process that constructs two SYCL
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queues on cslice sub-device #0. Kernels submitted to these two queues are
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guaranteed to conflict, both using the same set of execution units. Therefore,
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if a single process wants to explicitly submit kernels to cslice sub-devices
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and it wants to avoid conflict, it should create queues on different
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sub-devices. By contrast, consider an example where two separate processes
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create a SYCL queue on cslice sub-device #0. In this case, the device driver
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virtualizes access to this cslice, and kernels submitted from the first process
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may run on different execution units than kernels submitted from the second
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process. In this second case, the device driver binds the process's requested
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cslice to a physical cslice according to the overall system load.
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virtualizes work submission to different CCS-es, and this means that on
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Intel(R) Data Center GPU Max Series devices the work submission to a cslice is
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virtualized.) This virtualization happens only between processes, and not
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within a single process. For example, consider a single process that
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constructs two SYCL queues on cslice sub-device #0. Kernels submitted to these
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two queues are guaranteed to conflict, both using the same set of execution
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units. Therefore, if a single process wants to explicitly submit kernels to
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cslice sub-devices and it wants to avoid conflict, it should create queues on
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different sub-devices. By contrast, consider an example where two separate
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processes create a SYCL queue on cslice sub-device #0. In this case, the
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device driver virtualizes access to this cslice, and kernels submitted from the
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first process may run on different execution units than kernels submitted from
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the second process. In this second case, the device driver binds the process's
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requested cslice to a physical cslice according to the overall system load.
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Note that this extension can be supported by any implementation. If an
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implementation supports a backend or device without the concept of cslice

sycl/doc/extensions/supported/sycl_ext_intel_queue_index.asciidoc

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== Notice
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[%hardbreaks]
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Copyright (C) 2022-2022 Intel Corporation. All rights reserved.
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Copyright (C) 2022-2023 Intel Corporation. All rights reserved.
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Khronos(R) is a registered trademark and SYCL(TM) and SPIR(TM) are trademarks
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of The Khronos Group Inc. OpenCL(TM) is a trademark of Apple Inc. used by
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On many Intel devices, there is just one available queue index, and there is
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therefore no advantage to using the `compute_index` property. However, this
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property can sometimes be useful when running on Data Center GPU Flex series
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devices (aka ATS-M) or Data Center GPU Max series devices (aka PVC).
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devices (aka ATS-M) or Intel(R) Data Center GPU Max Series devices (aka PVC).
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Some models of ATS-M support multiple queue indices with the semantics
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described in the sections above. When a single process submits kernels to

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