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[DAGCombiner] Avoid the pre-truncate of BUILD_VECTOR sources. (#75792)
Avoid the pre-truncate of BUILD_VECTOR sources when there is more than one use. This can avoid using unnecessary movs later down the instruction selection pipeline.
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

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@@ -14759,6 +14759,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
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// Attempt to pre-truncate BUILD_VECTOR sources.
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if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
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N0.hasOneUse() &&
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TLI.isTruncateFree(SrcVT.getScalarType(), VT.getScalarType()) &&
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// Avoid creating illegal types if running after type legalizer.
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(!LegalTypes || TLI.isTypeLegal(VT.getScalarType()))) {

‎llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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define i32 @lower_lshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h) {
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; CHECK-LABEL: lower_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: addv s1, v1.4s
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; CHECK-NEXT: addv s4, v4.4s
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; CHECK-NEXT: addv s5, v5.4s
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; CHECK-NEXT: addv s2, v2.4s
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; CHECK-NEXT: addv s6, v6.4s
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; CHECK-NEXT: mov v0.s[1], v1.s[0]
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; CHECK-NEXT: addv s1, v3.4s
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; CHECK-NEXT: addv s3, v7.4s
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; CHECK-NEXT: mov v4.s[1], v5.s[0]
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; CHECK-NEXT: mov v0.s[2], v2.s[0]
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; CHECK-NEXT: mov v4.s[2], v6.s[0]
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; CHECK-NEXT: mov v0.s[3], v1.s[0]
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; CHECK-NEXT: mov v4.s[3], v3.s[0]
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; CHECK-NEXT: xtn v2.4h, v0.4s
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; CHECK-NEXT: shrn v0.4h, v0.4s, #16
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; CHECK-NEXT: xtn v1.4h, v4.4s
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; CHECK-NEXT: shrn v3.4h, v4.4s, #16
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; CHECK-NEXT: uhadd v0.4h, v2.4h, v0.4h
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; CHECK-NEXT: uhadd v1.4h, v1.4h, v3.4h
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; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
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; CHECK-NEXT: addv s0, v0.4s
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%l87 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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%l174 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b)
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%l257 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %c)
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%l340 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %d)
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%l427 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %e)
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%l514 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %f)
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%l597 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %g)
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%l680 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %h)
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%l681 = insertelement <8 x i32> poison, i32 %l87, i32 0
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%l682 = insertelement <8 x i32> %l681, i32 %l174, i32 1
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%l683 = insertelement <8 x i32> %l682, i32 %l257, i32 2
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%l684 = insertelement <8 x i32> %l683, i32 %l340, i32 3
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%l685 = insertelement <8 x i32> %l684, i32 %l427, i32 4
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%l686 = insertelement <8 x i32> %l685, i32 %l514, i32 5
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%l687 = insertelement <8 x i32> %l686, i32 %l597, i32 6
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%l688 = insertelement <8 x i32> %l687, i32 %l680, i32 7
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%l689 = and <8 x i32> %l688, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
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%l690 = lshr <8 x i32> %l688, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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%l691 = add nuw nsw <8 x i32> %l689, %l690
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%l692 = lshr <8 x i32> %l691, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%l693 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %l692)
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ret i32 %l693
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}
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) {
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; CHECK-LABEL: lower_trunc_16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: add x8, sp, #56
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; CHECK-NEXT: ld1r { v1.8h }, [x8]
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; CHECK-NEXT: mov v0.h[1], w1
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; CHECK-NEXT: add v3.8h, v1.8h, v1.8h
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; CHECK-NEXT: mov v0.h[2], w2
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; CHECK-NEXT: mov v0.h[3], w3
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; CHECK-NEXT: mov v0.h[4], w4
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; CHECK-NEXT: mov v0.h[5], w5
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; CHECK-NEXT: mov v0.h[6], w6
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; CHECK-NEXT: add v2.8h, v0.8h, v0.8h
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; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: uzp1 v1.16b, v2.16b, v3.16b
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%a1 = insertelement <16 x i16> poison, i16 %a, i16 0
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%b1 = insertelement <16 x i16> %a1, i16 %b, i16 1
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%c1 = insertelement <16 x i16> %b1, i16 %c, i16 2
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%d1 = insertelement <16 x i16> %c1, i16 %d, i16 3
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%e1 = insertelement <16 x i16> %d1, i16 %e, i16 4
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%f1 = insertelement <16 x i16> %e1, i16 %f, i16 5
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%g1 = insertelement <16 x i16> %f1, i16 %g, i16 6
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%h1 = insertelement <16 x i16> %g1, i16 %h, i16 7
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%i1 = insertelement <16 x i16> %f1, i16 %i, i16 8
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%j1 = insertelement <16 x i16> %g1, i16 %j, i16 9
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%k1 = insertelement <16 x i16> %f1, i16 %k, i16 10
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%l1 = insertelement <16 x i16> %g1, i16 %l, i16 11
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%m1 = insertelement <16 x i16> %f1, i16 %m, i16 12
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%n1 = insertelement <16 x i16> %g1, i16 %n, i16 13
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%o1 = insertelement <16 x i16> %f1, i16 %o, i16 14
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%p1 = insertelement <16 x i16> %g1, i16 %p, i16 15
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%t = trunc <16 x i16> %p1 to <16 x i8>
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%s = add <16 x i16> %p1, %p1
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%t2 = trunc <16 x i16> %s to <16 x i8>
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%pro = xor <16 x i8> %t, %t2
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ret <16 x i8> %pro
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}
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define <8 x i16> @lower_trunc_8xi16(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
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; CHECK-LABEL: lower_trunc_8xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w4
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: mov v0.s[1], w5
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; CHECK-NEXT: mov v1.s[1], w1
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; CHECK-NEXT: mov v0.s[2], w6
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; CHECK-NEXT: mov v1.s[2], w2
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; CHECK-NEXT: mov v0.s[3], w7
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; CHECK-NEXT: mov v1.s[3], w3
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; CHECK-NEXT: add v2.4s, v0.4s, v0.4s
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; CHECK-NEXT: add v3.4s, v1.4s, v1.4s
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; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: uzp1 v1.8h, v3.8h, v2.8h
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%a1 = insertelement <8 x i32> poison, i32 %a, i32 0
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%b1 = insertelement <8 x i32> %a1, i32 %b, i32 1
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%c1 = insertelement <8 x i32> %b1, i32 %c, i32 2
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%d1 = insertelement <8 x i32> %c1, i32 %d, i32 3
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%e1 = insertelement <8 x i32> %d1, i32 %e, i32 4
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%f1 = insertelement <8 x i32> %e1, i32 %f, i32 5
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%g1 = insertelement <8 x i32> %f1, i32 %g, i32 6
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%h1 = insertelement <8 x i32> %g1, i32 %h, i32 7
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%t = trunc <8 x i32> %h1 to <8 x i16>
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%s = add <8 x i32> %h1, %h1
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%t2 = trunc <8 x i32> %s to <8 x i16>
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%o = xor <8 x i16> %t, %t2
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ret <8 x i16> %o
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}
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define <4 x i32> @lower_trunc_4xi32(i64 %a, i64 %b, i64 %c, i64 %d) {
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; CHECK-LABEL: lower_trunc_4xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x2
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; CHECK-NEXT: fmov d1, x0
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; CHECK-NEXT: mov v0.d[1], x3
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; CHECK-NEXT: mov v1.d[1], x1
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; CHECK-NEXT: add v2.2d, v0.2d, v0.2d
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; CHECK-NEXT: add v3.2d, v1.2d, v1.2d
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; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: uzp1 v1.4s, v3.4s, v2.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%a1 = insertelement <4 x i64> poison, i64 %a, i64 0
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%b1 = insertelement <4 x i64> %a1, i64 %b, i64 1
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%c1 = insertelement <4 x i64> %b1, i64 %c, i64 2
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%d1 = insertelement <4 x i64> %c1, i64 %d, i64 3
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%t = trunc <4 x i64> %d1 to <4 x i32>
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%s = add <4 x i64> %d1, %d1
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%t2 = trunc <4 x i64> %s to <4 x i32>
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%o = xor <4 x i32> %t, %t2
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ret <4 x i32> %o
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}
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define <8 x i32> @lower_trunc_8xi32(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h) {
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; CHECK-LABEL: lower_trunc_8xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x2
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; CHECK-NEXT: fmov d1, x0
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; CHECK-NEXT: fmov d2, x6
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; CHECK-NEXT: fmov d3, x4
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; CHECK-NEXT: mov v0.d[1], x3
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; CHECK-NEXT: mov v1.d[1], x1
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; CHECK-NEXT: mov v2.d[1], x7
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; CHECK-NEXT: mov v3.d[1], x5
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; CHECK-NEXT: add v4.2d, v0.2d, v0.2d
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; CHECK-NEXT: add v5.2d, v1.2d, v1.2d
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; CHECK-NEXT: add v6.2d, v2.2d, v2.2d
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; CHECK-NEXT: add v7.2d, v3.2d, v3.2d
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; CHECK-NEXT: uzp1 v2.4s, v3.4s, v2.4s
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; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: uzp1 v3.4s, v5.4s, v4.4s
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; CHECK-NEXT: uzp1 v1.4s, v7.4s, v6.4s
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; CHECK-NEXT: eor v0.16b, v0.16b, v3.16b
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; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b
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; CHECK-NEXT: ret
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%a1 = insertelement <8 x i64> poison, i64 %a, i64 0
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%b1 = insertelement <8 x i64> %a1, i64 %b, i64 1
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%c1 = insertelement <8 x i64> %b1, i64 %c, i64 2
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%d1 = insertelement <8 x i64> %c1, i64 %d, i64 3
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%e1 = insertelement <8 x i64> %d1, i64 %e, i64 4
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%f1 = insertelement <8 x i64> %e1, i64 %f, i64 5
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%g1 = insertelement <8 x i64> %f1, i64 %g, i64 6
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%h1 = insertelement <8 x i64> %g1, i64 %h, i64 7
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%t = trunc <8 x i64> %h1 to <8 x i32>
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%s = add <8 x i64> %h1, %h1
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%t2 = trunc <8 x i64> %s to <8 x i32>
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%o = xor <8 x i32> %t, %t2
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ret <8 x i32> %o
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}

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