UefiCpuPkg: SmmProfile: Use public Architectural MSRs from MdePkg

Replaced local Msr defines with inclusion of Register/Amd/Msr.h.

Signed-off-by: Vivian Nowka-Keane <vnowkakeane@linux.microsoft.com>

Author: VivianNK

UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c

@@ -131,7 +131,13 @@ DisableBTS (
   VOID
   )
 {
-  AsmMsrAnd64 (MSR_DEBUG_CTL, ~((UINT64)(MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR)));
+  MSR_IA32_DEBUGCTL_REGISTER  DebugCtl;
+
+  DebugCtl.Uint64   = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
+  DebugCtl.Bits.BTS = 0;
+  DebugCtl.Bits.TR  = 0;
+
+  AsmWriteMsr64 (MSR_IA32_DEBUGCTL, DebugCtl.Uint64);
 }
 
 /**
@@ -143,7 +149,13 @@ EnableBTS (
   VOID
   )
 {
-  AsmMsrOr64 (MSR_DEBUG_CTL, (MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR));
+  MSR_IA32_DEBUGCTL_REGISTER  DebugCtl;
+
+  DebugCtl.Uint64   = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
+  DebugCtl.Bits.BTS = 1;
+  DebugCtl.Bits.TR  = 1;
+
+  AsmWriteMsr64 (MSR_IA32_DEBUGCTL, DebugCtl.Uint64);
 }
 
 /**
@@ -930,15 +942,15 @@ ActivateLBR (
   VOID
   )
 {
-  UINT64  DebugCtl;
+  MSR_IA32_DEBUGCTL_REGISTER  DebugCtl;
 
-  DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
-  if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {
+  DebugCtl.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
+  if (DebugCtl.Bits.LBR) {
     return;
   }
 
-  DebugCtl |= MSR_DEBUG_CTL_LBR;
-  AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
+  DebugCtl.Bits.LBR = 1;
+  AsmWriteMsr64 (MSR_IA32_DEBUGCTL, DebugCtl.Uint64);
 }
 
 /**
@@ -952,17 +964,23 @@ ActivateBTS (
   IN      UINTN  CpuIndex
   )
 {
-  UINT64  DebugCtl;
+  MSR_IA32_DEBUGCTL_REGISTER  DebugCtl;
 
-  DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
-  if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) {
+  DebugCtl.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
+  if ((DebugCtl.Bits.BTS)) {
     return;
   }
 
   AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]);
-  DebugCtl |= (UINT64)(MSR_DEBUG_CTL_BTS | MSR_DEBUG_CTL_TR);
-  DebugCtl &= ~((UINT64)MSR_DEBUG_CTL_BTINT);
-  AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
+
+  //
+  // Enable BTS
+  //
+  DebugCtl.Bits.BTS = 1;
+  DebugCtl.Bits.TR  = 1;
+
+  DebugCtl.Bits.BTINT = 0;
+  AsmWriteMsr64 (MSR_IA32_DEBUGCTL, DebugCtl.Uint64);
 }
 
 /**

UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h

@@ -39,20 +39,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 //
 // CPU generic definition
 //
-#define   MSR_EFER     0xc0000080
-#define   MSR_EFER_XD  0x800
+#define MSR_EFER_XD  0x800
 
-#define   CPUID1_EDX_BTS_AVAILABLE  0x200000
+#define CPUID1_EDX_BTS_AVAILABLE  0x200000
 
-#define   DR6_SINGLE_STEP  0x4000
-#define   RFLAG_TF         0x100
+#define DR6_SINGLE_STEP  0x4000
 
-#define MSR_DEBUG_CTL          0x1D9
-#define   MSR_DEBUG_CTL_LBR    0x1
-#define   MSR_DEBUG_CTL_TR     0x40
-#define   MSR_DEBUG_CTL_BTS    0x80
-#define   MSR_DEBUG_CTL_BTINT  0x100
-#define MSR_DS_AREA            0x600
+#define MSR_DS_AREA  0x600
 
 #define HEAP_GUARD_NONSTOP_MODE      \
         ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)