Getting Compilation error while doing make verilog

[krishna-yadu]

Hi,

I am trying out to generate the RTL core using Rocket chip for the first time. I followed all the steps and installed all the dependencies(not sure all are installed or not).

I was able to succesfully use Scala CLI to compile and run an example program.
But while running the make verilog inside rocket-chip, I am getting the below compilation error

/rocket-chip/dependencies/chisel/build.sc:34: trait Firrtl is abstract; cannot be instantiated
object firrtl extends CrossFirrtl

Is there anything I am missing here? Or should I use any other git branch?

Regards,
Yadu

[jerryz123]

For generating RTL of rocket-chip components, see Chipyard (chipyard.readthedocs.io).