@@ -80,6 +80,24 @@ using TileTypeIdx = UInt32;
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using TileTypeSiteTypeIdx = UInt32;
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using TileTypeSubTileIdx = UInt16;
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+ struct PIPTimingRef {
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+ type @0 :Ref.ReferenceType = parent;
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+ field @1 :Text = "pipTimingList" ;
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+ depth @2 :Int32 = 1 ;
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+
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+ }
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+ annotation pipTimingRef(*) :PIPTimingRef ;
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+ using PipTimingIdx = UInt32;
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+
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+ struct NodeTimingRef {
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+ type @0 :Ref.ReferenceType = parent;
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+ field @1 :Text = "nodeTimingList" ;
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+ depth @2 :Int32 = 1 ;
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+
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+ }
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+ annotation nodeTimingRef(*) :NodeTimingRef ;
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+ using NodeTimingIdx = UInt32;
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+
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struct Device {
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name @0 : Text;
@@ -102,6 +120,8 @@ struct Device {
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lutDefinitions @14 : LutDefinitions;
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parameterDefs @15 : ParameterDefinitions;
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wireTypes @16 : List(WireType);
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+ pipTimings @17 : List(PIPTiming);
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+ nodeTimings @18 : List(NodeTiming);
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# ######################################
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# Placement definition objects
@@ -213,12 +233,20 @@ struct Device {
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struct SitePIP {
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inpin @0 : BELPinIdx $belPinRef();
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outpin @1 : BELPinIdx $belPinRef();
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+ # Interconnect delay
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+ delay @2 : CornerModel;
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}
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struct SitePin {
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name @0 : StringIdx $stringRef();
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dir @1 : Dir.Netlist.Direction;
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belpin @2 : BELPinIdx $belPinRef();
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+ model : union {
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+ noModel @5 : Void;
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+ resistance @3 : CornerModel;
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+ capacitance @4 : CornerModel;
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+ }
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+ delay @6 : CornerModel;
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}
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# #####################################
@@ -250,7 +278,8 @@ struct Device {
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}
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struct Node {
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- wires @0 : List(WireIdx) $wireRef();
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+ wires @0 : List(WireIdx) $wireRef();
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+ nodeTiming @1 : NodeTimingIdx $nodeTimingRef();
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}
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struct PIP {
@@ -264,6 +293,7 @@ struct Device {
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pseudoCells @6 : List(PseudoCell);
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}
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subTile @7 : TileTypeSubTileIdx; # Index into Tile.subTilesPrefices
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+ timing @8 : PipTimingIdx $pipTimingRef();
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}
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struct PseudoCell {
@@ -297,7 +327,7 @@ struct Device {
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union {
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# Copy the value directly across with no transform applied
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copyValue @3 : Void;
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- # Apply an arbitrary mapping of bits while deriving the new value.
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+ # Apply an arbitrary mapping of bits while deriving the new value.
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# Bit i of the derived value will be taken from bit bitSlice[i] of the
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# parent primitive parameter. This way bit ranges; every Nth bit and
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# permutation can all be represented.
@@ -313,14 +343,14 @@ struct Device {
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# macro of the same name. This is also
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# used for conditional matches on
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# parameter values and parameter
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- # transforms from primitive to
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+ # transforms from primitive to
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# expansion.
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# #####################################
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struct PrimToMacroExpansion {
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primName @0 : StringIdx $stringRef();
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macroName @1 : StringIdx $stringRef();
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# Optionally, primitive to macro expansions can be conditional on a
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- # parameter match. For example, I/O buffer expansions might be
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+ # parameter match. For example, I/O buffer expansions might be
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# different between true and pseudo differential IO types. The
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# expansion is used if **any** of the parameters specified match.
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union {
@@ -339,6 +369,7 @@ struct Device {
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cell @0 : StringIdx $stringRef();
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commonPins @1 : List(CommonCellBelPinMaps);
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parameterPins @2 : List(ParameterCellBelPinMaps);
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+ pinsDelay @3 : List(PinsDelay);
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}
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# Map one cell pin to one BEL pin.
@@ -547,6 +578,123 @@ struct Device {
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cellPins @1 : List(CellPinInversion);
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}
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+ # #####################################
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+ # Timing modeling
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+ #
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+ # This section defines the timing model represantation
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+ # for the interchange schema.
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+ #
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+ # Even though there is no strict standard to define how many
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+ # corner models need to be defined for a given architecture,
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+ # a timing delay model usually includes a "fast" and a
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+ # "slow" corner process, each with three delay measures:
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+ # - minimum
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+ # - typical
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+ # - maximum
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+ #
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+ # The idea is to have a static definition of the corner models
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+ # so to standardize the interchange format to use at maximum
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+ # two process corner models (fast and slow), with the respective
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+ # delay measures. If an architecture does not include one or two
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+ # (but not all of three) delay measures, the timing model is still valid.
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+ #
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+ # There are three main location where timing delays must be defined:
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+ # - BEL/Cell pins
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+ # - Wires
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+ # - PIPs
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+ #
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+ # * BEL/Cell pins:
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+ # These delays can be sequential (associated to a clock pin) or combinatorial
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+ # (associated to an input/output pair).
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+ # At minimum there are four types of pin delays that need to be considered:
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+ # - comb : input to output delay
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+ # - setup : associated to the input and a clock pin
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+ # - hold : associated to the input and a clock pin
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+ # - clock2q : associated to the clock and the output pin
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+ #
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+ # * Wires:
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+ # These delays are associated to wires, or better nodes which are collection
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+ # of electrically connected wires.
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+ # They are described following the RC (Resistance/Capacitance) modeling.
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+ #
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+ # * PIPs:
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+ # These are delays corresponding to the connections between two wires.
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+ #
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+ # #####################################
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+
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+ # BEL/Cell pins delays
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+ struct PinsDelay {
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+ firstPin @0 : PinDelay;
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+ secondPin @1 : PinDelay;
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+ cornerModel @2 : CornerModel;
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+ pinsDelayType @3 : PinsDelayType;
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+ site @4 : SiteTypeIdx $siteTypeRef();
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+ }
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+
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+ struct PinDelay {
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+ pin @0 : BELPinIdx $belPinRef();
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+ union {
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+ noClock @1 : Void;
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+ clockEdge @2 : ClockEdge;
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+ }
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+ }
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+
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+ enum ClockEdge {
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+ rise @0 ;
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+ fall @1 ;
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+ }
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+
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+ enum PinsDelayType {
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+ comb @0 ;
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+ setup @1 ;
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+ hold @2 ;
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+ clk2q @3 ;
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+ }
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+
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+ # Wire (nodes) delays
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+ struct NodeTiming {
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+ capacitance @0 : CornerModel;
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+ resistance @1 : CornerModel;
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+ }
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+
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+ # PIP (switches) delays
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+ struct PIPTiming {
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+ inputCapacitance @0 : CornerModel;
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+ internalCapacitance @1 : CornerModel;
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+ internalDelay @2 : CornerModel;
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+ outputResistance @3 : CornerModel;
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+ outputCapacitance @4 : CornerModel;
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+ }
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+
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+ struct CornerModel {
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+ slow : union {
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+ noSlow @0 : Void;
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+ slow @1 : CornerModelValues;
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+ }
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+
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+ fast : union {
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+ noFast @2 : Void;
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+ fast @3 : CornerModelValues;
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+ }
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+ }
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+
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+ struct CornerModelValues {
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+ min : union {
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+ noMin @0 : Void;
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+ min @1 : Float32;
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+ }
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+
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+ typ : union {
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+ noTyp @2 : Void;
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+ typ @3 : Float32;
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+ }
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+
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+ max : union {
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+ noMax @4 : Void;
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+ max @5 : Float32;
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+ }
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+ }
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+
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# #####################################
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# Placement constraints
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#
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