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Merge pull request #38 from antmicro/initial-timing-structs-addition
device: add timing delay specification
2 parents ca10e82 + ba3d42c commit 78abf3f

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interchange/DeviceResources.capnp

Lines changed: 152 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,24 @@ using TileTypeIdx = UInt32;
8080
using TileTypeSiteTypeIdx = UInt32;
8181
using TileTypeSubTileIdx = UInt16;
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83+
struct PIPTimingRef {
84+
type @0 :Ref.ReferenceType = parent;
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field @1 :Text = "pipTimingList";
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depth @2 :Int32 = 1;
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}
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annotation pipTimingRef(*) :PIPTimingRef;
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using PipTimingIdx = UInt32;
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struct NodeTimingRef {
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type @0 :Ref.ReferenceType = parent;
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field @1 :Text = "nodeTimingList";
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depth @2 :Int32 = 1;
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}
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annotation nodeTimingRef(*) :NodeTimingRef;
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using NodeTimingIdx = UInt32;
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83101
struct Device {
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name @0 : Text;
@@ -102,6 +120,8 @@ struct Device {
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lutDefinitions @14 : LutDefinitions;
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parameterDefs @15 : ParameterDefinitions;
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wireTypes @16 : List(WireType);
123+
pipTimings @17 : List(PIPTiming);
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nodeTimings @18 : List(NodeTiming);
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#######################################
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# Placement definition objects
@@ -213,12 +233,20 @@ struct Device {
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struct SitePIP {
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inpin @0 : BELPinIdx $belPinRef();
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outpin @1 : BELPinIdx $belPinRef();
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# Interconnect delay
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delay @2 : CornerModel;
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}
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struct SitePin {
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name @0 : StringIdx $stringRef();
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dir @1 : Dir.Netlist.Direction;
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belpin @2 : BELPinIdx $belPinRef();
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model : union {
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noModel @5 : Void;
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resistance @3 : CornerModel;
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capacitance @4 : CornerModel;
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}
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delay @6 : CornerModel;
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}
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######################################
@@ -250,7 +278,8 @@ struct Device {
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}
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252280
struct Node {
253-
wires @0 : List(WireIdx) $wireRef();
281+
wires @0 : List(WireIdx) $wireRef();
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nodeTiming @1 : NodeTimingIdx $nodeTimingRef();
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}
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256285
struct PIP {
@@ -264,6 +293,7 @@ struct Device {
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pseudoCells @6 : List(PseudoCell);
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}
266295
subTile @7 : TileTypeSubTileIdx; # Index into Tile.subTilesPrefices
296+
timing @8 : PipTimingIdx $pipTimingRef();
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}
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269299
struct PseudoCell {
@@ -297,7 +327,7 @@ struct Device {
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union {
298328
# Copy the value directly across with no transform applied
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copyValue @3 : Void;
300-
# Apply an arbitrary mapping of bits while deriving the new value.
330+
# Apply an arbitrary mapping of bits while deriving the new value.
301331
# Bit i of the derived value will be taken from bit bitSlice[i] of the
302332
# parent primitive parameter. This way bit ranges; every Nth bit and
303333
# permutation can all be represented.
@@ -313,14 +343,14 @@ struct Device {
313343
# macro of the same name. This is also
314344
# used for conditional matches on
315345
# parameter values and parameter
316-
# transforms from primitive to
346+
# transforms from primitive to
317347
# expansion.
318348
######################################
319349
struct PrimToMacroExpansion {
320350
primName @0 : StringIdx $stringRef();
321351
macroName @1 : StringIdx $stringRef();
322352
# Optionally, primitive to macro expansions can be conditional on a
323-
# parameter match. For example, I/O buffer expansions might be
353+
# parameter match. For example, I/O buffer expansions might be
324354
# different between true and pseudo differential IO types. The
325355
# expansion is used if **any** of the parameters specified match.
326356
union {
@@ -339,6 +369,7 @@ struct Device {
339369
cell @0 : StringIdx $stringRef();
340370
commonPins @1 : List(CommonCellBelPinMaps);
341371
parameterPins @2 : List(ParameterCellBelPinMaps);
372+
pinsDelay @3 : List(PinsDelay);
342373
}
343374

344375
# Map one cell pin to one BEL pin.
@@ -547,6 +578,123 @@ struct Device {
547578
cellPins @1 : List(CellPinInversion);
548579
}
549580

581+
######################################
582+
# Timing modeling
583+
#
584+
# This section defines the timing model represantation
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# for the interchange schema.
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#
587+
# Even though there is no strict standard to define how many
588+
# corner models need to be defined for a given architecture,
589+
# a timing delay model usually includes a "fast" and a
590+
# "slow" corner process, each with three delay measures:
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# - minimum
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# - typical
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# - maximum
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#
595+
# The idea is to have a static definition of the corner models
596+
# so to standardize the interchange format to use at maximum
597+
# two process corner models (fast and slow), with the respective
598+
# delay measures. If an architecture does not include one or two
599+
# (but not all of three) delay measures, the timing model is still valid.
600+
#
601+
# There are three main location where timing delays must be defined:
602+
# - BEL/Cell pins
603+
# - Wires
604+
# - PIPs
605+
#
606+
# * BEL/Cell pins:
607+
# These delays can be sequential (associated to a clock pin) or combinatorial
608+
# (associated to an input/output pair).
609+
# At minimum there are four types of pin delays that need to be considered:
610+
# - comb : input to output delay
611+
# - setup : associated to the input and a clock pin
612+
# - hold : associated to the input and a clock pin
613+
# - clock2q : associated to the clock and the output pin
614+
#
615+
# * Wires:
616+
# These delays are associated to wires, or better nodes which are collection
617+
# of electrically connected wires.
618+
# They are described following the RC (Resistance/Capacitance) modeling.
619+
#
620+
# * PIPs:
621+
# These are delays corresponding to the connections between two wires.
622+
#
623+
######################################
624+
625+
# BEL/Cell pins delays
626+
struct PinsDelay {
627+
firstPin @0 : PinDelay;
628+
secondPin @1 : PinDelay;
629+
cornerModel @2 : CornerModel;
630+
pinsDelayType @3 : PinsDelayType;
631+
site @4 : SiteTypeIdx $siteTypeRef();
632+
}
633+
634+
struct PinDelay {
635+
pin @0 : BELPinIdx $belPinRef();
636+
union {
637+
noClock @1 : Void;
638+
clockEdge @2 : ClockEdge;
639+
}
640+
}
641+
642+
enum ClockEdge {
643+
rise @0;
644+
fall @1;
645+
}
646+
647+
enum PinsDelayType {
648+
comb @0;
649+
setup @1;
650+
hold @2;
651+
clk2q @3;
652+
}
653+
654+
# Wire (nodes) delays
655+
struct NodeTiming {
656+
capacitance @0 : CornerModel;
657+
resistance @1 : CornerModel;
658+
}
659+
660+
# PIP (switches) delays
661+
struct PIPTiming {
662+
inputCapacitance @0 : CornerModel;
663+
internalCapacitance @1 : CornerModel;
664+
internalDelay @2 : CornerModel;
665+
outputResistance @3 : CornerModel;
666+
outputCapacitance @4 : CornerModel;
667+
}
668+
669+
struct CornerModel {
670+
slow : union {
671+
noSlow @0 : Void;
672+
slow @1 : CornerModelValues;
673+
}
674+
675+
fast : union {
676+
noFast @2 : Void;
677+
fast @3 : CornerModelValues;
678+
}
679+
}
680+
681+
struct CornerModelValues {
682+
min : union {
683+
noMin @0 : Void;
684+
min @1 : Float32;
685+
}
686+
687+
typ : union {
688+
noTyp @2 : Void;
689+
typ @3 : Float32;
690+
}
691+
692+
max : union {
693+
noMax @4 : Void;
694+
max @5 : Float32;
695+
}
696+
}
697+
550698
######################################
551699
# Placement constraints
552700
#

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