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coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA #120

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coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA#120
@chithize

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@chithize
chithize
opened on Oct 26, 2023

HI ,

I tried test cmark, dhrystone testing with latest VeeR EH1, for ICCM, high_perf target, no way can get 4.9 claimed by WD before.
any special compiler or rtl source config needed?

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