RISCV extension support - bitmainip Zba/Zbb/Zbc/Zbs #2697
Description
Feature
- New architecture module
- Support for processor extension
- Add more instruction details (elaborated below)
- Binding support for:
language - Other (elaborated below)
Describe the feature you'd like
Support RISC-V bitmanip extension.
Additional context
At this point, almost all RISC-V processors support partial or full bitmanip extension. The presence of such instruction is not rare anymore. gcc can automatically generate such when Zba/Zbb/Zbc/Zbs are enabled. Also the linux kernel uses it in string functions, e.g., https://elixir.bootlin.com/linux/v6.14.5/source/arch/riscv/lib/strcmp.S#L74
https://elixir.bootlin.com/linux/v6.14.5/source/arch/riscv/lib/strlen.S#L82
It'll be very nice for capstone to support such instructions. Thanks