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cfallincfallin
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Merge pull request #2019 from akirilov-arm/show_freg_sized
AArch64: Remove show_freg_sized()
2 parents 4ba3ee3 + 4006392 commit bc1e960

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2 files changed

+48
-59
lines changed

2 files changed

+48
-59
lines changed

‎cranelift/codegen/src/isa/aarch64/inst/mod.rs

Lines changed: 40 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -2509,7 +2509,7 @@ impl Inst {
25092509
ScalarSize::Size64 => F64,
25102510
_ => unimplemented!(),
25112511
};
2512-
let rd = show_freg_sized(rd.to_reg(), mb_rru, size);
2512+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
25132513
let rn = show_vreg_element(rn, mb_rru, idx, vector_type);
25142514
format!("mov {}, {}", rd, rn)
25152515
}
@@ -2524,8 +2524,8 @@ impl Inst {
25242524
FPUOp1::Cvt32To64 => ("fcvt", ScalarSize::Size32, ScalarSize::Size64),
25252525
FPUOp1::Cvt64To32 => ("fcvt", ScalarSize::Size64, ScalarSize::Size32),
25262526
};
2527-
let rd = show_freg_sized(rd.to_reg(), mb_rru, sizedest);
2528-
let rn = show_freg_sized(rn, mb_rru, sizesrc);
2527+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, sizedest);
2528+
let rn = show_vreg_scalar(rn, mb_rru, sizesrc);
25292529
format!("{} {}, {}", op, rd, rn)
25302530
}
25312531
&Inst::FpuRRR { fpu_op, rd, rn, rm } => {
@@ -2543,9 +2543,9 @@ impl Inst {
25432543
FPUOp2::Min32 => ("fmin", ScalarSize::Size32),
25442544
FPUOp2::Min64 => ("fmin", ScalarSize::Size64),
25452545
};
2546-
let rd = show_freg_sized(rd.to_reg(), mb_rru, size);
2547-
let rn = show_freg_sized(rn, mb_rru, size);
2548-
let rm = show_freg_sized(rm, mb_rru, size);
2546+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
2547+
let rn = show_vreg_scalar(rn, mb_rru, size);
2548+
let rm = show_vreg_scalar(rm, mb_rru, size);
25492549
format!("{} {}, {}, {}", op, rd, rn, rm)
25502550
}
25512551
&Inst::FpuRRI { fpu_op, rd, rn } => {
@@ -2559,7 +2559,7 @@ impl Inst {
25592559
let show_vreg_fn: fn(Reg, Option<&RealRegUniverse>) -> String = if vector {
25602560
|reg, mb_rru| show_vreg_vector(reg, mb_rru, F32X2)
25612561
} else {
2562-
|reg, mb_rru| show_vreg_scalar(reg, mb_rru, F64)
2562+
|reg, mb_rru| show_vreg_scalar(reg, mb_rru, ScalarSize::Size64)
25632563
};
25642564
let rd = show_vreg_fn(rd.to_reg(), mb_rru);
25652565
let rn = show_vreg_fn(rn, mb_rru);
@@ -2576,30 +2576,30 @@ impl Inst {
25762576
FPUOp3::MAdd32 => ("fmadd", ScalarSize::Size32),
25772577
FPUOp3::MAdd64 => ("fmadd", ScalarSize::Size64),
25782578
};
2579-
let rd = show_freg_sized(rd.to_reg(), mb_rru, size);
2580-
let rn = show_freg_sized(rn, mb_rru, size);
2581-
let rm = show_freg_sized(rm, mb_rru, size);
2582-
let ra = show_freg_sized(ra, mb_rru, size);
2579+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
2580+
let rn = show_vreg_scalar(rn, mb_rru, size);
2581+
let rm = show_vreg_scalar(rm, mb_rru, size);
2582+
let ra = show_vreg_scalar(ra, mb_rru, size);
25832583
format!("{} {}, {}, {}, {}", op, rd, rn, rm, ra)
25842584
}
25852585
&Inst::FpuCmp32 { rn, rm } => {
2586-
let rn = show_freg_sized(rn, mb_rru, ScalarSize::Size32);
2587-
let rm = show_freg_sized(rm, mb_rru, ScalarSize::Size32);
2586+
let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size32);
2587+
let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size32);
25882588
format!("fcmp {}, {}", rn, rm)
25892589
}
25902590
&Inst::FpuCmp64 { rn, rm } => {
2591-
let rn = show_freg_sized(rn, mb_rru, ScalarSize::Size64);
2592-
let rm = show_freg_sized(rm, mb_rru, ScalarSize::Size64);
2591+
let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size64);
2592+
let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size64);
25932593
format!("fcmp {}, {}", rn, rm)
25942594
}
25952595
&Inst::FpuLoad32 { rd, ref mem, .. } => {
2596-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size32);
2596+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size32);
25972597
let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
25982598
let mem = mem.show_rru(mb_rru);
25992599
format!("{}ldr {}, {}", mem_str, rd, mem)
26002600
}
26012601
&Inst::FpuLoad64 { rd, ref mem, .. } => {
2602-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size64);
2602+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
26032603
let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
26042604
let mem = mem.show_rru(mb_rru);
26052605
format!("{}ldr {}, {}", mem_str, rd, mem)
@@ -2612,13 +2612,13 @@ impl Inst {
26122612
format!("{}ldr {}, {}", mem_str, rd, mem)
26132613
}
26142614
&Inst::FpuStore32 { rd, ref mem, .. } => {
2615-
let rd = show_freg_sized(rd, mb_rru, ScalarSize::Size32);
2615+
let rd = show_vreg_scalar(rd, mb_rru, ScalarSize::Size32);
26162616
let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
26172617
let mem = mem.show_rru(mb_rru);
26182618
format!("{}str {}, {}", mem_str, rd, mem)
26192619
}
26202620
&Inst::FpuStore64 { rd, ref mem, .. } => {
2621-
let rd = show_freg_sized(rd, mb_rru, ScalarSize::Size64);
2621+
let rd = show_vreg_scalar(rd, mb_rru, ScalarSize::Size64);
26222622
let (mem_str, mem) = mem_finalize_for_show(mem, mb_rru, state);
26232623
let mem = mem.show_rru(mb_rru);
26242624
format!("{}str {}, {}", mem_str, rd, mem)
@@ -2631,15 +2631,15 @@ impl Inst {
26312631
format!("{}str {}, {}", mem_str, rd, mem)
26322632
}
26332633
&Inst::LoadFpuConst32 { rd, const_data } => {
2634-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size32);
2634+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size32);
26352635
format!("ldr {}, pc+8 ; b 8 ; data.f32 {}", rd, const_data)
26362636
}
26372637
&Inst::LoadFpuConst64 { rd, const_data } => {
2638-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size64);
2638+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
26392639
format!("ldr {}, pc+8 ; b 12 ; data.f64 {}", rd, const_data)
26402640
}
26412641
&Inst::LoadFpuConst128 { rd, const_data } => {
2642-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size128);
2642+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size128);
26432643
format!("ldr {}, pc+8 ; b 20 ; data.f128 0x{:032x}", rd, const_data)
26442644
}
26452645
&Inst::FpuToInt { op, rd, rn } => {
@@ -2654,7 +2654,7 @@ impl Inst {
26542654
FpuToIntOp::F64ToU64 => ("fcvtzu", ScalarSize::Size64, OperandSize::Size64),
26552655
};
26562656
let rd = show_ireg_sized(rd.to_reg(), mb_rru, sizedest);
2657-
let rn = show_freg_sized(rn, mb_rru, sizesrc);
2657+
let rn = show_vreg_scalar(rn, mb_rru, sizesrc);
26582658
format!("{} {}, {}", op, rd, rn)
26592659
}
26602660
&Inst::IntToFpu { op, rd, rn } => {
@@ -2668,21 +2668,21 @@ impl Inst {
26682668
IntToFpuOp::I64ToF64 => ("scvtf", OperandSize::Size64, ScalarSize::Size64),
26692669
IntToFpuOp::U64ToF64 => ("ucvtf", OperandSize::Size64, ScalarSize::Size64),
26702670
};
2671-
let rd = show_freg_sized(rd.to_reg(), mb_rru, sizedest);
2671+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, sizedest);
26722672
let rn = show_ireg_sized(rn, mb_rru, sizesrc);
26732673
format!("{} {}, {}", op, rd, rn)
26742674
}
26752675
&Inst::FpuCSel32 { rd, rn, rm, cond } => {
2676-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size32);
2677-
let rn = show_freg_sized(rn, mb_rru, ScalarSize::Size32);
2678-
let rm = show_freg_sized(rm, mb_rru, ScalarSize::Size32);
2676+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size32);
2677+
let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size32);
2678+
let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size32);
26792679
let cond = cond.show_rru(mb_rru);
26802680
format!("fcsel {}, {}, {}, {}", rd, rn, rm, cond)
26812681
}
26822682
&Inst::FpuCSel64 { rd, rn, rm, cond } => {
2683-
let rd = show_freg_sized(rd.to_reg(), mb_rru, ScalarSize::Size64);
2684-
let rn = show_freg_sized(rn, mb_rru, ScalarSize::Size64);
2685-
let rm = show_freg_sized(rm, mb_rru, ScalarSize::Size64);
2683+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ScalarSize::Size64);
2684+
let rn = show_vreg_scalar(rn, mb_rru, ScalarSize::Size64);
2685+
let rm = show_vreg_scalar(rm, mb_rru, ScalarSize::Size64);
26862686
let cond = cond.show_rru(mb_rru);
26872687
format!("fcsel {}, {}, {}, {}", rd, rn, rm, cond)
26882688
}
@@ -2697,8 +2697,8 @@ impl Inst {
26972697
FpuRoundMode::Nearest32 => ("frintn", ScalarSize::Size32),
26982698
FpuRoundMode::Nearest64 => ("frintn", ScalarSize::Size64),
26992699
};
2700-
let rd = show_freg_sized(rd.to_reg(), mb_rru, size);
2701-
let rn = show_freg_sized(rn, mb_rru, size);
2700+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
2701+
let rn = show_vreg_scalar(rn, mb_rru, size);
27022702
format!("{} {}, {}", inst, rd, rn)
27032703
}
27042704
&Inst::MovToVec64 { rd, rn } => {
@@ -2790,7 +2790,7 @@ impl Inst {
27902790
let show_vreg_fn: fn(Reg, Option<&RealRegUniverse>, Type) -> String = if vector {
27912791
|reg, mb_rru, ty| show_vreg_vector(reg, mb_rru, ty)
27922792
} else {
2793-
|reg, mb_rru, _ty| show_vreg_scalar(reg, mb_rru, I64)
2793+
|reg, mb_rru, _ty| show_vreg_scalar(reg, mb_rru, ScalarSize::Size64)
27942794
};
27952795

27962796
let rd = show_vreg_fn(rd.to_reg(), mb_rru, ty);
@@ -2812,8 +2812,14 @@ impl Inst {
28122812
let op = match op {
28132813
VecLanesOp::Uminv => "uminv",
28142814
};
2815+
let size = match ty {
2816+
I8X16 => ScalarSize::Size8,
2817+
I16X8 => ScalarSize::Size16,
2818+
I32X4 => ScalarSize::Size32,
2819+
_ => unimplemented!(),
2820+
};
28152821

2816-
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, ty);
2822+
let rd = show_vreg_scalar(rd.to_reg(), mb_rru, size);
28172823
let rn = show_vreg_vector(rn, mb_rru, ty);
28182824
format!("{} {}, {}", op, rd, rn)
28192825
}

‎cranelift/codegen/src/isa/aarch64/inst/regs.rs

Lines changed: 8 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -277,25 +277,8 @@ pub fn show_ireg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: Operand
277277
s
278278
}
279279

280-
/// Show a vector register.
281-
pub fn show_freg_sized(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: ScalarSize) -> String {
282-
let mut s = reg.show_rru(mb_rru);
283-
if reg.get_class() != RegClass::V128 {
284-
return s;
285-
}
286-
let prefix = match size {
287-
ScalarSize::Size8 => "b",
288-
ScalarSize::Size16 => "h",
289-
ScalarSize::Size32 => "s",
290-
ScalarSize::Size64 => "d",
291-
ScalarSize::Size128 => "q",
292-
};
293-
s.replace_range(0..1, prefix);
294-
s
295-
}
296-
297280
/// Show a vector register used in a scalar context.
298-
pub fn show_vreg_scalar(reg: Reg, mb_rru: Option<&RealRegUniverse>, ty: Type) -> String {
281+
pub fn show_vreg_scalar(reg: Reg, mb_rru: Option<&RealRegUniverse>, size: ScalarSize) -> String {
299282
let mut s = reg.show_rru(mb_rru);
300283
if reg.get_class() != RegClass::V128 {
301284
// We can't do any better.
@@ -304,13 +287,13 @@ pub fn show_vreg_scalar(reg: Reg, mb_rru: Option<&RealRegUniverse>, ty: Type) ->
304287

305288
if reg.is_real() {
306289
// Change (eg) "v0" into "d0".
307-
if reg.get_class() == RegClass::V128 && s.starts_with("v") {
308-
let replacement = match ty {
309-
I64 | F64 => "d",
310-
I8X16 => "b",
311-
I16X8 => "h",
312-
I32X4 => "s",
313-
_ => unimplemented!(),
290+
if s.starts_with("v") {
291+
let replacement = match size {
292+
ScalarSize::Size8 => "b",
293+
ScalarSize::Size16 => "h",
294+
ScalarSize::Size32 => "s",
295+
ScalarSize::Size64 => "d",
296+
ScalarSize::Size128 => "q",
314297
};
315298
s.replace_range(0..1, replacement);
316299
}

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