Purpose of the TRST and Power pin on Blackpill design

[TaurusEight]

I'm attempting build a BMP from a Blackpill but I have a few questions concerning the purpose of both the PA6 pin marked TRST and PA1 pin marked Power. I have been referencing the schematic file 'bmpm_v2_1e_schematic.pdf' and I was wondering if the TRST pin is the iRST_SENSE line and the Power pin is the PWR_BR line.

-A

[dragonmux]

Current generation Black Magic Probe itself does not expose or provide ~TRST, only ~RST which is what the iRST_SENSE line is about. ~TRST is the JTAG Test Reset pin and is only found on some pinouts for JTAG (excluding ARM's 10-pin pinout, but such as their older pre-trace 20-pin pinout). This pin only resets the JTAG state machine, which is usually achieved via clocking the same state machine with TCK while holding TMS high for at least 5 cycles. The design of the JTAG state machine guarantees this is the exact same operation as pulsing ~TRST would be.

You are correct that power control is achieved on BMP via the PWR_BR line. Do note that for Black Pill, the common code for the platform defines all the critical pinout things expected by those 3 platforms.

[TaurusEight]

Thank you for the clarification. I should have mentioned I was also using the README file in the common code section for the Blackpills. Now just to be certain I understand pin PA1, the Power Pin, this connects to the VCC pin on the JTAG-10 and to the dual-bit dual-supply bus transceivers used with the various output lines.

Why is this Power pin needed? Could the supplied voltage come from the 3v3 supply instead?

[dragonmux]

Ohh, we see - uh, so it's not a first-party supported platform (it's community supported) but at best guess based on the definitions in the platform header, it's for controlling a MOSFET to allow you to implement control via the tpwr monitor command for whether a target is being fed power or not by the Black Pill.

You may very well not want to always have power being supplied by the probe on the JTAG connector, especially as many many targets supply their own resulting in dangerous backfeeding - this pin on the debug connector is supposed to be for a reference voltage from the target, so supplying power from the probe is an overloaded use that is outside the original intended use of the pin. Feel free to ignore it if you don't intend to implement power control, but note just hard wiring 3.3V to the Vtgt pin while what many knock-off debuggers do, is not officially sanctioned usage and carries backfeeding risks on compliant targets.

[ALTracer]

To add, yes, blackpill-f4 is very loosely related to native BMP schematics, if only in function; PA5 is System reset output (open-drain active-low) controlled by platform callback, PA6 is JTAG Test Reset output (push-pull active-low) controlled by jtagtap.c, PA1 is "Enable some power to the target".

Tangent: TRST_PIN could still be useful for some microcontrollers which have their TRST input pulled down -- to pull it up and activate the normally deactivated JTAG logic. Most STM32 MCUs are not like this, they internally pull up TRST and JTAG is immediately available (but board designers can put an external resistor pull-down). While jtagtap_reset() will yank it down, it will still emit the soft-reset sequence, and you might as well put an external jumper between TRST and Vdd if your target requires that for debug access.

PA1 is an optional PWR_BR output pin active-high (when SHIELD=1 makeflag is used) to control a MOSFET (power switch) which connects ... something, it can be as complicated as a second LDO to VTpwr, or as simple as blackpills' own primary LDO (3.3v) to VTpwr (VTref?), to power up and provide a few 100mA to small targets (please check schematics and LDO ratings for how much). It's convenient to power up a second blackpill, for example, but it might brownout the first chip during the transient (there's no PWM soft-start implemented, only BMP does this). Idea: connect 5v Vbus to 5v_in of the DUT's LDO if possible, just don't mix it up with 3.3v Vddio pins of either chip. Or you can do everything yourself via external flywires or power cables.

Unfortunately, there's to VTref ADC readout implemented, as the blackpill PCB has no resistive divider, that'd be external and may vary from user to user. But also there's no voltage-translating buffers out of the box, only 3.3v Vddio targets are supported (3.0-3.6v?)

[dragonmux]

Tangent: TRST_PIN could still be useful for some microcontrollers which have their TRST input pulled down -- to pull it up and activate the normally deactivated JTAG logic. Most STM32 MCUs are not like this, they internally pull up TRST and JTAG is immediately available (but board designers can put an external resistor pull-down). While jtagtap_reset() will yank it down, it will still emit the soft-reset sequence, and you might as well put an external jumper between TRST and Vdd if your target requires that for debug access.

While a good point, we would also point out that this is only relevant when the board exposes the signal to its debug connector, which necessitates using an older pinout. For example the pre-Cortex ARM debug connector pinout or SEGGER's pre-Cortex pinout

[TaurusEight]

I was wondering why the version 2.1e schematics would connect the TRST_PIN to the RST pin through a Mosfet. If the TRST_PIN is only useful on pre-Cortex connectors why include it in the design? I do not have access to the schematics for v2.3, so I don't know if this pin is still connected.

My projects use small STM32s and clone chips. I've purchased several v2.3 probes from iBitSquared but I also like building my own tools. I have previously built probes using Bluepills and now I want to build one using an STM32F411CE based Blackpill.

[dragonmux]

Ah, we see your confusion - you've got PA1 vs PB1 mixed. That said, PB1 should not be being used for TRST on the current generation hardware so that's a problem in itself we need to fix.

PA1 is nRST is connected via a MOSFET to the nRST pin on the connector so BMP can safely pulse it low using open-drain logic.

[TaurusEight]

Going back to version 2_1e of the Blackmagic Probe schematics I am having trouble understanding the purpose of routing pin PB1, PWR_BR, through a Duel P-Channel Mosfet, specifically the DMG1023uv-7 labeled as Q1.

Is the purpose to keep the VCC pin of the JTAG-10 at 3v3 when PB1 is Low or when it is High? And why use a duel P-Channel mosfet? Wouldn't a single mosfet or transistor work just as well?

I understand this ties into the tpwr monitor command.

[dragonmux]

Hi @TaurusEight so.. there are two parts to your question really.. we'll answer the second first as it'll help things make more sense:

The dual pFET is used to prevent backflow in both directions when not enabled. Otherwise the target would backfeed the BMP power supply, or BMP would backfeed the target - both of which are potentially bad news.

The way that PWR_BR works is that when low (off), the pFETs are turned on hard (-3.3Vgs) and conduct, shunting the 3.3V regulator to VTgt; when high (on), the pFETs are turned hard off (0Vgs) and hold the two thoroughly separated from each other.

To understand why the use of two pFETs is required here, please look at the theory on how the body diode of a FET works and interacts in this situation.

[TaurusEight]

Thank you.

Pin 3 of Q1 connects to the VCC pin of JTAG-10, but it also connects to PWR_FLAG. Is this to add access to the 4u7 capacitor as a bypass capacitor? Would it not be better to provide a 100nF capacitor directory on the JTAG-10 VCC pin?

[dragonmux]

PWR_FLAG is a special marker in KiCad for telling its ERC where power is coming from - it has no functional purpose and can be ignored from that perspective.

[TaurusEight]

Thank you.