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Automerge: [InstCombine] Add tests for moving exts across identity shuffles.
Also merges redundant check lines in PhaseOrdering/X86/blendv-select.ll to reduce test diff in upcoming change. Precommits tests for llvm/llvm-project#146901.
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‎llvm/test/Transforms/InstCombine/fold-shuffle-ext.ll

Lines changed: 121 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,121 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2+
; RUN: opt -p instcombine -S %s | FileCheck %s
3+
4+
define <4 x i16> @ext_identity_mask_first_vector_first_half_4xi16(<8 x i8> %x) {
5+
; CHECK-LABEL: define <4 x i16> @ext_identity_mask_first_vector_first_half_4xi16(
6+
; CHECK-SAME: <8 x i8> [[X:%.*]]) {
7+
; CHECK-NEXT: [[ENTRY:.*:]]
8+
; CHECK-NEXT: [[E_1:%.*]] = zext <8 x i8> [[X]] to <8 x i16>
9+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[E_1]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
10+
; CHECK-NEXT: ret <4 x i16> [[SHUFFLE]]
11+
;
12+
entry:
13+
%e.1 = zext <8 x i8> %x to <8 x i16>
14+
%shuffle = shufflevector <8 x i16> %e.1, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
15+
ret <4 x i16> %shuffle
16+
}
17+
18+
define <3 x i32> @ext_identity_mask_first_vector_first_half_3xi32(<4 x i16> %x) {
19+
; CHECK-LABEL: define <3 x i32> @ext_identity_mask_first_vector_first_half_3xi32(
20+
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
21+
; CHECK-NEXT: [[ENTRY:.*:]]
22+
; CHECK-NEXT: [[E_1:%.*]] = zext <4 x i16> [[X]] to <4 x i32>
23+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[E_1]], <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
24+
; CHECK-NEXT: ret <3 x i32> [[SHUFFLE]]
25+
;
26+
entry:
27+
%e.1 = zext <4 x i16> %x to <4 x i32>
28+
%shuffle = shufflevector <4 x i32> %e.1, <4 x i32> poison, <3 x i32> <i32 0, i32 1, i32 2>
29+
ret <3 x i32> %shuffle
30+
}
31+
32+
define <4 x i16> @ext_no_identity_mask1(<8 x i8> %in) {
33+
; CHECK-LABEL: define <4 x i16> @ext_no_identity_mask1(
34+
; CHECK-SAME: <8 x i8> [[IN:%.*]]) {
35+
; CHECK-NEXT: [[ENTRY:.*:]]
36+
; CHECK-NEXT: [[E_1:%.*]] = zext <8 x i8> [[IN]] to <8 x i16>
37+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[E_1]], <8 x i16> poison, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
38+
; CHECK-NEXT: ret <4 x i16> [[SHUFFLE]]
39+
;
40+
entry:
41+
%e.1 = zext <8 x i8> %in to <8 x i16>
42+
%shuffle = shufflevector <8 x i16> %e.1, <8 x i16> poison, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
43+
ret <4 x i16> %shuffle
44+
}
45+
46+
define <4 x i16> @ext_no_identity_mask2(<8 x i8> %x, <8 x i16> %y) {
47+
; CHECK-LABEL: define <4 x i16> @ext_no_identity_mask2(
48+
; CHECK-SAME: <8 x i8> [[X:%.*]], <8 x i16> [[Y:%.*]]) {
49+
; CHECK-NEXT: [[ENTRY:.*:]]
50+
; CHECK-NEXT: [[E_1:%.*]] = zext <8 x i8> [[X]] to <8 x i16>
51+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[E_1]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
52+
; CHECK-NEXT: ret <4 x i16> [[SHUFFLE]]
53+
;
54+
entry:
55+
%e.1 = zext <8 x i8> %x to <8 x i16>
56+
%shuffle = shufflevector <8 x i16> %e.1, <8 x i16> %y, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
57+
ret <4 x i16> %shuffle
58+
}
59+
60+
define <5 x i32> @ext_identity_mask_first_vector_first_half_5xi32(<4 x i16> %x) {
61+
; CHECK-LABEL: define <5 x i32> @ext_identity_mask_first_vector_first_half_5xi32(
62+
; CHECK-SAME: <4 x i16> [[X:%.*]]) {
63+
; CHECK-NEXT: [[ENTRY:.*:]]
64+
; CHECK-NEXT: [[E_1:%.*]] = zext <4 x i16> [[X]] to <4 x i32>
65+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[E_1]], <4 x i32> poison, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0>
66+
; CHECK-NEXT: ret <5 x i32> [[SHUFFLE]]
67+
;
68+
entry:
69+
%e.1 = zext <4 x i16> %x to <4 x i32>
70+
%shuffle = shufflevector <4 x i32> %e.1, <4 x i32> %e.1, <5 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4>
71+
ret <5 x i32> %shuffle
72+
}
73+
74+
define <4 x i16> @ext_no_identity_mask_first_vector_second_half(<8 x i8> %x, <8 x i16> %y) {
75+
; CHECK-LABEL: define <4 x i16> @ext_no_identity_mask_first_vector_second_half(
76+
; CHECK-SAME: <8 x i8> [[X:%.*]], <8 x i16> [[Y:%.*]]) {
77+
; CHECK-NEXT: [[ENTRY:.*:]]
78+
; CHECK-NEXT: [[E_1:%.*]] = zext <8 x i8> [[X]] to <8 x i16>
79+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[E_1]], <8 x i16> [[Y]], <4 x i32> <i32 0, i32 9, i32 1, i32 10>
80+
; CHECK-NEXT: ret <4 x i16> [[SHUFFLE]]
81+
;
82+
entry:
83+
%e.1 = zext <8 x i8> %x to <8 x i16>
84+
%shuffle = shufflevector <8 x i16> %e.1, <8 x i16> %y, <4 x i32> <i32 0, i32 9, i32 1, i32 10>
85+
ret <4 x i16> %shuffle
86+
}
87+
88+
define <4 x i16> @select_second_op(<8 x i8> %x, <8 x i16> %y) {
89+
; CHECK-LABEL: define <4 x i16> @select_second_op(
90+
; CHECK-SAME: <8 x i8> [[X:%.*]], <8 x i16> [[Y:%.*]]) {
91+
; CHECK-NEXT: [[ENTRY:.*:]]
92+
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[Y]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
93+
; CHECK-NEXT: ret <4 x i16> [[SHUFFLE]]
94+
;
95+
entry:
96+
%e.1 = zext <8 x i8> %x to <8 x i16>
97+
%shuffle = shufflevector <8 x i16> %e.1, <8 x i16> %y, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
98+
ret <4 x i16> %shuffle
99+
}
100+
101+
define <4 x i32> @load_i32_zext_to_v4i32(ptr %di) {
102+
; CHECK-LABEL: define <4 x i32> @load_i32_zext_to_v4i32(
103+
; CHECK-SAME: ptr [[DI:%.*]]) {
104+
; CHECK-NEXT: [[ENTRY:.*:]]
105+
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[DI]], align 4
106+
; CHECK-NEXT: [[VEC_INS:%.*]] = insertelement <2 x i32> <i32 poison, i32 0>, i32 [[L]], i64 0
107+
; CHECK-NEXT: [[VEC_BC:%.*]] = bitcast <2 x i32> [[VEC_INS]] to <8 x i8>
108+
; CHECK-NEXT: [[E_1:%.*]] = zext <8 x i8> [[VEC_BC]] to <8 x i16>
109+
; CHECK-NEXT: [[VEC_SHUFFLE:%.*]] = shufflevector <8 x i16> [[E_1]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
110+
; CHECK-NEXT: [[EXT_2:%.*]] = zext nneg <4 x i16> [[VEC_SHUFFLE]] to <4 x i32>
111+
; CHECK-NEXT: ret <4 x i32> [[EXT_2]]
112+
;
113+
entry:
114+
%l = load i32, ptr %di
115+
%vec.ins = insertelement <2 x i32> <i32 poison, i32 0>, i32 %l, i64 0
116+
%vec.bc = bitcast <2 x i32> %vec.ins to <8 x i8>
117+
%e.1 = zext <8 x i8> %vec.bc to <8 x i16>
118+
%vec.shuffle = shufflevector <8 x i16> %e.1, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
119+
%ext.2 = zext nneg <4 x i16> %vec.shuffle to <4 x i32>
120+
ret <4 x i32> %ext.2
121+
}

‎llvm/test/Transforms/PhaseOrdering/X86/blendv-select.ll

Lines changed: 30 additions & 100 deletions
Original file line numberDiff line numberDiff line change
@@ -12,20 +12,10 @@
1212
;
1313

1414
define <4 x double> @x86_pblendvb_v4f64_v2f64(<4 x double> %a, <4 x double> %b, <4 x double> %c, <4 x double> %d) {
15-
; SSE-LABEL: @x86_pblendvb_v4f64_v2f64(
16-
; SSE-NEXT: [[TMP1:%.*]] = fcmp olt <4 x double> [[C:%.*]], [[D:%.*]]
17-
; SSE-NEXT: [[DOTV:%.*]] = select <4 x i1> [[TMP1]], <4 x double> [[B:%.*]], <4 x double> [[A:%.*]]
18-
; SSE-NEXT: ret <4 x double> [[DOTV]]
19-
;
20-
; AVX2-LABEL: @x86_pblendvb_v4f64_v2f64(
21-
; AVX2-NEXT: [[TMP1:%.*]] = fcmp olt <4 x double> [[C:%.*]], [[D:%.*]]
22-
; AVX2-NEXT: [[DOTV:%.*]] = select <4 x i1> [[TMP1]], <4 x double> [[B:%.*]], <4 x double> [[A:%.*]]
23-
; AVX2-NEXT: ret <4 x double> [[DOTV]]
24-
;
25-
; AVX512-LABEL: @x86_pblendvb_v4f64_v2f64(
26-
; AVX512-NEXT: [[CMP:%.*]] = fcmp olt <4 x double> [[C:%.*]], [[D:%.*]]
27-
; AVX512-NEXT: [[DOTV:%.*]] = select <4 x i1> [[CMP]], <4 x double> [[B:%.*]], <4 x double> [[A:%.*]]
28-
; AVX512-NEXT: ret <4 x double> [[DOTV]]
15+
; CHECK-LABEL: @x86_pblendvb_v4f64_v2f64(
16+
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <4 x double> [[C:%.*]], [[D:%.*]]
17+
; CHECK-NEXT: [[DOTV:%.*]] = select <4 x i1> [[CMP]], <4 x double> [[B:%.*]], <4 x double> [[A:%.*]]
18+
; CHECK-NEXT: ret <4 x double> [[DOTV]]
2919
;
3020
%a.bc = bitcast <4 x double> %a to <32 x i8>
3121
%b.bc = bitcast <4 x double> %b to <32 x i8>
@@ -46,20 +36,10 @@ define <4 x double> @x86_pblendvb_v4f64_v2f64(<4 x double> %a, <4 x double> %b,
4636
}
4737

4838
define <8 x float> @x86_pblendvb_v8f32_v4f32(<8 x float> %a, <8 x float> %b, <8 x float> %c, <8 x float> %d) {
49-
; SSE-LABEL: @x86_pblendvb_v8f32_v4f32(
50-
; SSE-NEXT: [[TMP1:%.*]] = fcmp olt <8 x float> [[C:%.*]], [[D:%.*]]
51-
; SSE-NEXT: [[DOTV:%.*]] = select <8 x i1> [[TMP1]], <8 x float> [[B:%.*]], <8 x float> [[A:%.*]]
52-
; SSE-NEXT: ret <8 x float> [[DOTV]]
53-
;
54-
; AVX2-LABEL: @x86_pblendvb_v8f32_v4f32(
55-
; AVX2-NEXT: [[TMP1:%.*]] = fcmp olt <8 x float> [[C:%.*]], [[D:%.*]]
56-
; AVX2-NEXT: [[DOTV:%.*]] = select <8 x i1> [[TMP1]], <8 x float> [[B:%.*]], <8 x float> [[A:%.*]]
57-
; AVX2-NEXT: ret <8 x float> [[DOTV]]
58-
;
59-
; AVX512-LABEL: @x86_pblendvb_v8f32_v4f32(
60-
; AVX512-NEXT: [[CMP:%.*]] = fcmp olt <8 x float> [[C:%.*]], [[D:%.*]]
61-
; AVX512-NEXT: [[DOTV:%.*]] = select <8 x i1> [[CMP]], <8 x float> [[B:%.*]], <8 x float> [[A:%.*]]
62-
; AVX512-NEXT: ret <8 x float> [[DOTV]]
39+
; CHECK-LABEL: @x86_pblendvb_v8f32_v4f32(
40+
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt <8 x float> [[C:%.*]], [[D:%.*]]
41+
; CHECK-NEXT: [[DOTV:%.*]] = select <8 x i1> [[CMP]], <8 x float> [[B:%.*]], <8 x float> [[A:%.*]]
42+
; CHECK-NEXT: ret <8 x float> [[DOTV]]
6343
;
6444
%a.bc = bitcast <8 x float> %a to <32 x i8>
6545
%b.bc = bitcast <8 x float> %b to <32 x i8>
@@ -80,20 +60,10 @@ define <8 x float> @x86_pblendvb_v8f32_v4f32(<8 x float> %a, <8 x float> %b, <8
8060
}
8161

8262
define <4 x i64> @x86_pblendvb_v4i64_v2i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) {
83-
; SSE-LABEL: @x86_pblendvb_v4i64_v2i64(
84-
; SSE-NEXT: [[TMP1:%.*]] = icmp slt <4 x i64> [[C:%.*]], [[D:%.*]]
85-
; SSE-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i64> [[B:%.*]], <4 x i64> [[A:%.*]]
86-
; SSE-NEXT: ret <4 x i64> [[TMP2]]
87-
;
88-
; AVX2-LABEL: @x86_pblendvb_v4i64_v2i64(
89-
; AVX2-NEXT: [[TMP1:%.*]] = icmp slt <4 x i64> [[C:%.*]], [[D:%.*]]
90-
; AVX2-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i64> [[B:%.*]], <4 x i64> [[A:%.*]]
91-
; AVX2-NEXT: ret <4 x i64> [[TMP2]]
92-
;
93-
; AVX512-LABEL: @x86_pblendvb_v4i64_v2i64(
94-
; AVX512-NEXT: [[CMP:%.*]] = icmp slt <4 x i64> [[C:%.*]], [[D:%.*]]
95-
; AVX512-NEXT: [[TMP1:%.*]] = select <4 x i1> [[CMP]], <4 x i64> [[B:%.*]], <4 x i64> [[A:%.*]]
96-
; AVX512-NEXT: ret <4 x i64> [[TMP1]]
63+
; CHECK-LABEL: @x86_pblendvb_v4i64_v2i64(
64+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <4 x i64> [[C:%.*]], [[D:%.*]]
65+
; CHECK-NEXT: [[TMP1:%.*]] = select <4 x i1> [[CMP]], <4 x i64> [[B:%.*]], <4 x i64> [[A:%.*]]
66+
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
9767
;
9868
%a.bc = bitcast <4 x i64> %a to <32 x i8>
9969
%b.bc = bitcast <4 x i64> %b to <32 x i8>
@@ -216,35 +186,15 @@ define <4 x i64> @x86_pblendvb_v16i16_v8i16(<4 x i64> %a, <4 x i64> %b, <4 x i64
216186
}
217187

218188
define <4 x i64> @x86_pblendvb_v32i8_v16i8(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c, <4 x i64> %d) {
219-
; SSE-LABEL: @x86_pblendvb_v32i8_v16i8(
220-
; SSE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
221-
; SSE-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[B:%.*]] to <32 x i8>
222-
; SSE-NEXT: [[C_BC:%.*]] = bitcast <4 x i64> [[C:%.*]] to <32 x i8>
223-
; SSE-NEXT: [[D_BC:%.*]] = bitcast <4 x i64> [[D:%.*]] to <32 x i8>
224-
; SSE-NEXT: [[TMP3:%.*]] = icmp slt <32 x i8> [[C_BC]], [[D_BC]]
225-
; SSE-NEXT: [[CONCAT:%.*]] = select <32 x i1> [[TMP3]], <32 x i8> [[TMP2]], <32 x i8> [[TMP1]]
226-
; SSE-NEXT: [[RES:%.*]] = bitcast <32 x i8> [[CONCAT]] to <4 x i64>
227-
; SSE-NEXT: ret <4 x i64> [[RES]]
228-
;
229-
; AVX2-LABEL: @x86_pblendvb_v32i8_v16i8(
230-
; AVX2-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
231-
; AVX2-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[B:%.*]] to <32 x i8>
232-
; AVX2-NEXT: [[C_BC:%.*]] = bitcast <4 x i64> [[C:%.*]] to <32 x i8>
233-
; AVX2-NEXT: [[D_BC:%.*]] = bitcast <4 x i64> [[D:%.*]] to <32 x i8>
234-
; AVX2-NEXT: [[TMP3:%.*]] = icmp slt <32 x i8> [[C_BC]], [[D_BC]]
235-
; AVX2-NEXT: [[CONCAT:%.*]] = select <32 x i1> [[TMP3]], <32 x i8> [[TMP2]], <32 x i8> [[TMP1]]
236-
; AVX2-NEXT: [[RES:%.*]] = bitcast <32 x i8> [[CONCAT]] to <4 x i64>
237-
; AVX2-NEXT: ret <4 x i64> [[RES]]
238-
;
239-
; AVX512-LABEL: @x86_pblendvb_v32i8_v16i8(
240-
; AVX512-NEXT: [[A_BC:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
241-
; AVX512-NEXT: [[B_BC:%.*]] = bitcast <4 x i64> [[B:%.*]] to <32 x i8>
242-
; AVX512-NEXT: [[C_BC:%.*]] = bitcast <4 x i64> [[C:%.*]] to <32 x i8>
243-
; AVX512-NEXT: [[D_BC:%.*]] = bitcast <4 x i64> [[D:%.*]] to <32 x i8>
244-
; AVX512-NEXT: [[CMP:%.*]] = icmp slt <32 x i8> [[C_BC]], [[D_BC]]
245-
; AVX512-NEXT: [[CONCAT:%.*]] = select <32 x i1> [[CMP]], <32 x i8> [[B_BC]], <32 x i8> [[A_BC]]
246-
; AVX512-NEXT: [[RES:%.*]] = bitcast <32 x i8> [[CONCAT]] to <4 x i64>
247-
; AVX512-NEXT: ret <4 x i64> [[RES]]
189+
; CHECK-LABEL: @x86_pblendvb_v32i8_v16i8(
190+
; CHECK-NEXT: [[A_BC:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
191+
; CHECK-NEXT: [[B_BC:%.*]] = bitcast <4 x i64> [[B:%.*]] to <32 x i8>
192+
; CHECK-NEXT: [[C_BC:%.*]] = bitcast <4 x i64> [[C:%.*]] to <32 x i8>
193+
; CHECK-NEXT: [[D_BC:%.*]] = bitcast <4 x i64> [[D:%.*]] to <32 x i8>
194+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <32 x i8> [[C_BC]], [[D_BC]]
195+
; CHECK-NEXT: [[CONCAT:%.*]] = select <32 x i1> [[CMP]], <32 x i8> [[B_BC]], <32 x i8> [[A_BC]]
196+
; CHECK-NEXT: [[RES:%.*]] = bitcast <32 x i8> [[CONCAT]] to <4 x i64>
197+
; CHECK-NEXT: ret <4 x i64> [[RES]]
248198
;
249199
%a.bc = bitcast <4 x i64> %a to <32 x i8>
250200
%b.bc = bitcast <4 x i64> %b to <32 x i8>
@@ -424,35 +374,15 @@ define <8 x i64> @x86_pblendvb_v32i16_v16i16(<8 x i64> %a, <8 x i64> %b, <8 x i6
424374
}
425375

426376
define <8 x i64> @x86_pblendvb_v64i8_v32i8(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c, <8 x i64> %d) {
427-
; SSE-LABEL: @x86_pblendvb_v64i8_v32i8(
428-
; SSE-NEXT: [[TMP1:%.*]] = bitcast <8 x i64> [[A:%.*]] to <64 x i8>
429-
; SSE-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[B:%.*]] to <64 x i8>
430-
; SSE-NEXT: [[C_BC:%.*]] = bitcast <8 x i64> [[C:%.*]] to <64 x i8>
431-
; SSE-NEXT: [[D_BC:%.*]] = bitcast <8 x i64> [[D:%.*]] to <64 x i8>
432-
; SSE-NEXT: [[TMP3:%.*]] = icmp slt <64 x i8> [[C_BC]], [[D_BC]]
433-
; SSE-NEXT: [[CONCAT:%.*]] = select <64 x i1> [[TMP3]], <64 x i8> [[TMP2]], <64 x i8> [[TMP1]]
434-
; SSE-NEXT: [[RES:%.*]] = bitcast <64 x i8> [[CONCAT]] to <8 x i64>
435-
; SSE-NEXT: ret <8 x i64> [[RES]]
436-
;
437-
; AVX2-LABEL: @x86_pblendvb_v64i8_v32i8(
438-
; AVX2-NEXT: [[TMP1:%.*]] = bitcast <8 x i64> [[A:%.*]] to <64 x i8>
439-
; AVX2-NEXT: [[TMP2:%.*]] = bitcast <8 x i64> [[B:%.*]] to <64 x i8>
440-
; AVX2-NEXT: [[C_BC:%.*]] = bitcast <8 x i64> [[C:%.*]] to <64 x i8>
441-
; AVX2-NEXT: [[D_BC:%.*]] = bitcast <8 x i64> [[D:%.*]] to <64 x i8>
442-
; AVX2-NEXT: [[TMP3:%.*]] = icmp slt <64 x i8> [[C_BC]], [[D_BC]]
443-
; AVX2-NEXT: [[CONCAT:%.*]] = select <64 x i1> [[TMP3]], <64 x i8> [[TMP2]], <64 x i8> [[TMP1]]
444-
; AVX2-NEXT: [[RES:%.*]] = bitcast <64 x i8> [[CONCAT]] to <8 x i64>
445-
; AVX2-NEXT: ret <8 x i64> [[RES]]
446-
;
447-
; AVX512-LABEL: @x86_pblendvb_v64i8_v32i8(
448-
; AVX512-NEXT: [[A_BC:%.*]] = bitcast <8 x i64> [[A:%.*]] to <64 x i8>
449-
; AVX512-NEXT: [[B_BC:%.*]] = bitcast <8 x i64> [[B:%.*]] to <64 x i8>
450-
; AVX512-NEXT: [[C_BC:%.*]] = bitcast <8 x i64> [[C:%.*]] to <64 x i8>
451-
; AVX512-NEXT: [[D_BC:%.*]] = bitcast <8 x i64> [[D:%.*]] to <64 x i8>
452-
; AVX512-NEXT: [[CMP:%.*]] = icmp slt <64 x i8> [[C_BC]], [[D_BC]]
453-
; AVX512-NEXT: [[CONCAT:%.*]] = select <64 x i1> [[CMP]], <64 x i8> [[B_BC]], <64 x i8> [[A_BC]]
454-
; AVX512-NEXT: [[RES:%.*]] = bitcast <64 x i8> [[CONCAT]] to <8 x i64>
455-
; AVX512-NEXT: ret <8 x i64> [[RES]]
377+
; CHECK-LABEL: @x86_pblendvb_v64i8_v32i8(
378+
; CHECK-NEXT: [[A_BC:%.*]] = bitcast <8 x i64> [[A:%.*]] to <64 x i8>
379+
; CHECK-NEXT: [[B_BC:%.*]] = bitcast <8 x i64> [[B:%.*]] to <64 x i8>
380+
; CHECK-NEXT: [[C_BC:%.*]] = bitcast <8 x i64> [[C:%.*]] to <64 x i8>
381+
; CHECK-NEXT: [[D_BC:%.*]] = bitcast <8 x i64> [[D:%.*]] to <64 x i8>
382+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <64 x i8> [[C_BC]], [[D_BC]]
383+
; CHECK-NEXT: [[CONCAT:%.*]] = select <64 x i1> [[CMP]], <64 x i8> [[B_BC]], <64 x i8> [[A_BC]]
384+
; CHECK-NEXT: [[RES:%.*]] = bitcast <64 x i8> [[CONCAT]] to <8 x i64>
385+
; CHECK-NEXT: ret <8 x i64> [[RES]]
456386
;
457387
%a.bc = bitcast <8 x i64> %a to <64 x i8>
458388
%b.bc = bitcast <8 x i64> %b to <64 x i8>

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